IDDQ Testing of Submicron CMOS—by Cooling?

The usability of I DDQ testing is limited by the subthreshold currents of the low-V T, submicron MOS transistors in the low bias voltage circuits. The paper addresses the cooling of the chip in order to overcome this problem. Experimental results concerning the effect of cooling on the threshold voltage and subthreshold current are presented in the range of –75...25 Centigrade. The subthreshold currents decrease by a factor of about 100–1000 by cooling-down the chip to –75 Centigrade

IDDQ testing of submicron CMOS by cooling

International audienceThe usability of IDDQ testing is limited by the subthreshold currents of the low-VT, submicron MOS transistors in the low bias voltage circuits. The paper addresses the cooling of the chip in order to overcome this problem. Experimental results concerning the effect of cooling on the threshold voltage and subthreshold current are presented in the range of -75...25 Celsius. The subthreshold currents decrease by a factor of about 100 by cooling-down the chip to -75 Celsius