IC-processed micro-motors: design, technology, and testing

Micro-motors having rotors with diameters between 60 and 120 μm have been fabricated and driven electrostatically to continuous rotation. These motors were built using processes derived from IC (integrated circuit) microcircuit fabrication techniques. Initial tests on the motors show that friction plays a dominant role in their dynamic behavior. Observed rotational speeds have thus far been limited to several hundred r.p.m., which is a small fraction of what would be achievable if only natural frequency were to limit the response. Experimental starting voltages are at least an order of magnitude larger than had been expected (60 V at minimum and above 100 V for some structures). Observations of asynchronous as well as synchronous rotation between the driving fields and the rotors can be explained in terms of the torque/rotor-angle characteristics for the motors

Near-Optimal and Robust Mechanism Design for Covering Problems with Correlated Players

We consider the problem of designing incentive-compatible, ex-post individually rational (IR) mechanisms for covering problems in the Bayesian setting, where players' types are drawn from an underlying distribution and may be correlated, and the goal is to minimize the expected total payment made by the mechanism. We formulate a notion of incentive compatibility (IC) that we call {\em support-based IC} that is substantially more robust than Bayesian IC, and develop black-box reductions from support-based-IC mechanism design to algorithm design. For single-dimensional settings, this black-box reduction applies even when we only have an LP-relative {\em approximation algorithm} for the algorithmic problem. Thus, we obtain near-optimal mechanisms for various covering settings including single-dimensional covering problems, multi-item procurement auctions, and multidimensional facility location.Comment: Major changes compared to the previous version. Please consult this versio

Requirements for a Research-oriented IC Design System

Computer-aided design techniques for integrated circuits grown in an incremental way, responding to various perceived needs, so that today there are a number of useful programs for logic generation, simulation at various levels, test preparation, artwork generation and analysis (including design rule checking), and interactive graphical editing. While the design of many circuits has benefitted from these programs, when industry wants to produce a high-volume part, the design and layout are done manually, followed by digitizing and perhaps some graphic editing before it is converted to pattern generation format, leading to the often heard statement that computer-aided design of integrated circuits doesn't work. If progress is to be made, it seems clear that the entire design process has to be thought through in basic terms, and much more attention must be paid to the way in which computational techniques can complement the designer's abilities. Currently, it is appropriate to try to characterize the design process in abstract terms, so that implementation and technological biases don't cloud the view of a desired system. In this paper, we briefly describe the conversion of algorithms to masks at a very general level, and then describe several projects at MIT which aim to provide contributions to an integrated design system. It is emphasized that no complete system design exists now at MIT, and that we believe that general design considerations must constantly be tested by building (and rebuilding) the various subcomponents, the structure of which is guided by our view of the overall design process

Analog IC Design at the University of Twente

This article describes some recent research results from the IC Design group of the University of Twente, located in Enschede, The Netherlands.\ud \ud Our research focuses on analog CMOS circuit design with emphasis on high frequency and broadband circuits. With the trend of system integration in mind, we try to develop new circuit techniques that enable the next steps in system integration in nanometer CMOS technology. Our research funding comes from industry, as well as from governmental organizations. We aim to find fundamental solutions for practical problems of integrated circuits realized in industrial Silicon technologies.\ud \ud CMOS IC technology is dictated by optimal cost and performance of digital circuits and is certainly not optimized for nice analog behavior. As analog designers, we do not have the illusion to be able to change the CMOS technology, so we have to "live with it" and solve the problems by design. In this article several examples will be shown, where problematic analog behavior, such as noise and distortion, can be tackled with new circuit design techniques. These circuit techniques are developed in such a way that they do benefit from the modern technology and thus enable further integration. This way we can improve various analog building blocks for wireless, wire-line and optical communication. Below some examples are given.\ud \u

Immersion on the Edge: A Cooperative Framework for Mobile Immersive Computing

Immersive computing (IC) technologies such as virtual reality and augmented reality are gaining tremendous popularity. In this poster, we present CoIC, a Cooperative framework for mobile Immersive Computing. The design of CoIC is based on a key insight that IC tasks among different applications or users might be similar or redundant. CoIC enhances the performance of mobile IC applications by caching and sharing computation-intensive IC results on the edge. Our preliminary evaluation results on an AR application show that CoIC can reduce the recognition and rendering latency by up to 52.28% and 75.86% respectively on current mobile devices.Comment: This poster has been accepted by the SIGCOMM in June 201

Validation by Measurements of a IC Modeling Approach for SiP Applications

The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern systemin-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysi

Irreducible incoherence and intelligent design : a look into the conceptual toolbox of a pseudoscience

The concept of Irreducible Complexity (IC) has played a pivotal role in the resurgence of the creationist movement over the past two decades. Evolutionary biologists and philosophers have unambiguously rejected the purported demonstration of “intelligent design” in nature, but there have been several, apparently contradictory, lines of criticism. We argue that this is in fact due to Michael Behe's own incoherent definition and use of IC. This paper offers an analysis of several equivocations inherent in the concept of Irreducible Complexity and discusses the way in which advocates of the Intelligent Design Creationism (IDC) have conveniently turned IC into a moving target. An analysis of these rhetorical strategies helps us to understand why IC has gained such prominence in the IDC movement, and why, despite its complete lack of scientific merits, it has even convinced some knowledgeable persons of the impending demise of evolutionary theory

Reusing Logic Masking to Facilitate Hardware Trojan Detection

Hardware Trojan (HT) and Integrated Circuit (IC)/ Intellectual Property (IP) piracy are important threats which may happen in untrusted fabrication foundries. Modifying structurally the ICs/IPs design to counter the HT threats has been proposed, and it is known as Design-For-Hardware-Trust (DFHT). DFHT methods are used in order to facilitate HT detection methods. In addition, logic masking methods modify the IPs/ICs design to harden them against the IP/IC piracy. These methods modify a circuit such that it does not work correctly without applying the correct key. In this paper, we propose DFHT methods leveraging logic masking approach