IC performance prediction system

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.Includes bibliographical references.Issued also on microfiche from Lange Micrographics.In a mixed-product semiconductor foundry, optimization of product binning, packaging, product quantity control and rapid problem diagnosis are all critical to economic success. Binning is the placement of chips into several different specification categories. Binning has traditionally been done on the basis of performance (e.g. ,speed, operating range). For maximum profit, it must be accurately determined which specification bin a chip ties in. The integrated circuit pack-age makes up a large fraction of total product cost, and has a major influence on product performance and reliability. To minimize packaging costs, packaging has to be selected according to how a chip will be binned. Performance prediction is also important for product control and when the chip is to be packaged away from the foundry, such as when it will be used in Multi-Chip Module (MCM). The difficulty in achieving these goals is that there is limited data available at the time each decision must be made. For example, performance banning and package selection must be done after the water-level electrical test, but the water test is not a thorough performance test. The current practice is to accept some loss of profits due to imperfect predictions that result in under-specified and over-packaged products, additional failures in final test, a mismatch of product supply and demand, or additional yield loss. The IC performance prediction system (IPPS) proposed in this research will use primarily wafer-level functional and parametric electrical test data, supplemented with in-line and in-situ data to make performance predictions. Based on the waterlevel parametric test, we will predict chip performance in order to select the appropriate package. Predictions that fall outside acceptable limits will be used for process diagnosis purposes. We will use the predicted performance to determine additional wafer starts necessary to meet product demand. This can be coupled with equipment utilization to predict and minimize fabrication costs