I/O Scheduling Schemes for Better I/O Proportionality on Flash-based SSDs

In cloud computing, multiple servers are consolidated into a physical machine in order to reduce the cost of deploying the servers. Guaranteeing the service level objective (SLO) of each server is one of the most important factors in a virtualization system. Particularly, isolating the I/O resources among VMs competing for a shared storage system is challenging. Recently, use of flash based Solid State Drives (SSDs) is being extended to enterprise systems. However, there are few studies for guaranteeing SLOs on such systems. In this paper, we empirically analyze the I/O behavior of a shared SSD. We show that performance SLOs of storage systems employing SSDs being shared by VMs or tasks are not satisfactory. We analyze and show that components of SSDs such as channels, DRAM buffer, and Native Command Queuing (NCQ) are the reasons behind this problem. Based on these analysis and observations, we propose two SSD-aware host level I/O schedulers that we call A+CFQ and H+BFQ, which are extensions of state-of-the-art I/O schedulers CFQ and BFQ, respectively. Through implementation and experiments on Linux, we show that the proposed I/O schedulers improve proportionality without sacrifice to performance

Managing contamination delay to improve Timing Speculation architectures

Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact