Abstract We present an algorithm for assigning off-chip I/O pads for a logic circuit. The technique which is based on the analysis of the circuit structure and path delay constraints, uses linear placement, goal-programming, linear-sum assignment and I/O pad clustering to as- sign locations to I/O pads. The I/O pad assignment is then used by placement tools. Experimental data shows that as a result of using our I/O pad assign- ment procedure, the total interconnection length and circuit delay (after placement and routing) are reduced by 8-15 % and 3-4 % respectively