5 research outputs found

    Power Optimized CNN Based CAM Using Clock Gating Techniques

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    A Content Addressable Memory(CAM) is a Memory used in certain very high speed searchapplications. It compares input data against a table of stored data, and returns the address of matching data.Since basic look up table functions performed overall the stored memory information there is a high power dissipation. The proposed clock gating technique to reduce the power consumption. Since delay buffers are accessed sequentially, it adopts ring counter addressing scheme. In the ring counter D- Flip flops are usedare utilized to reduce power consumptio

    FPGA based Ternary Content Addressable Memory using SRAM

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    Hybrid-type CAM design for both power and performance efficiency

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    Content-addressable memory (CAM) is a hardware table that can compare the search data with all the stored data in parallel. Due to the parallel comparison feature where a large amount of transistors are active on each lookup, however, the power consumption of CAM is usually considerable. This paper presents a hybrid-type CAM design which aims to combine the performance advantage of the NOR-type CAM with the power efficiency of the NAND-type CAM. In our design, a CAM word is divided into two segments, and then all the CAM cells are decoupled from the match line. By minimizing both the match line capacitances and switching activities, our design can largely reduce the power consumption of CAM. The experimental results show that the hybrid-type CAM can reduce the search energy consumption by roughly 89% compared to the traditional NOR-type CAM. Because the hybrid-type CAM provides a fast pull-down path to speed up the lightweight match line discharge, the search performance of our design is even better than that of the traditional NOR-type CAM
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