A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture

The stringent power budget of fine grained power managed digital integrated circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. The scheduling also aims at maximum resource sharing and is able to attain sufficient area and power gains for complex benchmarks when timing constraints are relaxed by sufficient amount. Experimental results show that the algorithm that operates without any user constraint(area/power) is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.Comment: 18 pages, 6 figures, International journal of VLSI design & Communication Systems (VLSICS

Integrated functions among multiple starch synthases determine both amylopectin chain length and branch linkage location in Arabidopsis leaf starch

This study assessed the impact on starch metabolism in Arabidopsis leaves of simultaneously eliminating multiple soluble starch synthases (SS) from among SS1, SS2, and SS3. Double mutant ss1- ss2- or ss1- ss3- lines were generated using confirmed null mutations. These were compared to the wild type, each single mutant, and ss1- ss2- ss3- triple mutant lines grown in standardized environments. Double mutant plants developed similarly to the wild type, although they accumulated less leaf starch in both short-day and long-day diurnal cycles. Despite the reduced levels in the double mutants, lines containing only SS2 and SS4, or SS3 and SS4, are able to produce substantial amounts of starch granules. In both double mutants the residual starch was structurally modified including higher ratios of amylose:amylopectin, altered glucan chain length distribution within amylopectin, abnormal granule morphology, and altered placement of α(1→6) branch linkages relative to the reducing end of each linear chain. The data demonstrate that SS activity affects not only chain elongation but also the net result of branch placement accomplished by the balanced activities of starch branching enzymes and starch debranching enzymes. SS3 was shown partially to overlap in function with SS1 for the generation of short glucan chains within amylopectin. Compensatory functions that, in some instances, allow continued residual starch production in the absence of specific SS classes were identified, probaby accomplished by the granule bound starch synthase GBSS1.ANR Génoplante GPLA0611GEuropean Union-FEDER, Région Nord Pas de Calais ARCir PlantTEQ5National Science Foundation DBI-0209789Comisión Interministerial de Ciencia y Tecnología BIO2009-07040Junta de Andalucía P09-CVI-470

Functional characteristics of a double positive feedback loop coupled with autorepression

We study the functional characteristics of a two-gene motif consisting of a double positive feedback loop and an autoregulatory negative feedback loop. The motif appears in the gene regulatory network controlling the functional activity of pancreatic $\beta$-cells. The model exhibits bistability and hysteresis in appropriate parameter regions. The two stable steady states correspond to low (OFF state) and high (ON state) protein levels respectively. Using a deterministic approach, we show that the region of bistability increases in extent when the copy number of one of the genes is reduced from two to one. The negative feedback loop has the effect of reducing the size of the bistable region. Loss of a gene copy, brought about by mutations, hampers the normal functioning of the $\beta$-cells giving rise to the genetic disorder, maturity-onset diabetes of the young (MODY). The diabetic phenotype makes its appearance when a sizable fraction of the $\beta$-cells is in the OFF state. Using stochastic simulation techniques, we show that, on reduction of the gene copy number, there is a transition from the monostable ON to the ON state in the bistable region of the parameter space. Fluctuations in the protein levels, arising due to the stochastic nature of gene expression, can give rise to transitions between the ON and OFF states. We show that as the strength of autorepression increases, the ON$\to$OFF state transitions become less probable whereas the reverse transitions are more probable. The implications of the results in the context of the occurrence of MODY are pointed out..Comment: 9 pages 14 figure

PPH dendrimers grafted on silica nanoparticles: surface chemistry, characterization, silver colloids hosting and antibacterial activity

Polyphosphorhydrazone (PPH) dendrimers have been grafted on silica nanoparticles, and the surface functions of the dendrimers have been derivatized to phosphonates with lateral poly(ethyleneglycol) (PEG) chains. All materials have been thoroughly characterized by MAS NMR, FT-IR, electron microscopy, TGA and elemental analysis. These materials successfully hosted silver and silver oxide nanoparticles. The resulting composites exhibit antibacterial activity

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

On cost-effective reuse of components in the design of complex reconfigurable systems

Design strategies that benefit from the reuse of system components can reduce costs while maintaining or increasing dependability—we use the term dependability to tie together reliability and availability. D3H2 (aDaptive Dependable Design for systems with Homogeneous and Heterogeneous redundancies) is a methodology that supports the design of complex systems with a focus on reconfiguration and component reuse. D3H2 systematizes the identification of heterogeneous redundancies and optimizes the design of fault detection and reconfiguration mechanisms, by enabling the analysis of design alternatives with respect to dependability and cost. In this paper, we extend D3H2 for application to repairable systems. The method is extended with analysis capabilities allowing dependability assessment of complex reconfigurable systems. Analysed scenarios include time-dependencies between failure events and the corresponding reconfiguration actions. We demonstrate how D3H2 can support decisions about fault detection and reconfiguration that seek to improve dependability while reducing costs via application to a realistic railway case study

A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem

The Task Graph Cost-Optimal Scheduling Problem consists in scheduling a certain number of interdependent tasks onto a set of heterogeneous processors (characterized by idle and running rates per time unit), minimizing the cost of the entire process. This paper provides a novel formulation for this scheduling puzzle, in which an optimal solution is computed through a sequence of Binate Covering Problems, hinged within a Bounded Model Checking paradigm. In this approach, each covering instance, providing a min-cost trace for a given schedule depth, can be solved with several strategies, resorting to Minimum-Cost Satisfiability solvers or Pseudo-Boolean Optimization tools. Unfortunately, all direct resolution methods show very low efficiency and scalability. As a consequence, we introduce a specialized method to solve the same sequence of problems, based on a traditional all-solution SAT solver. This approach follows the "circuit cofactoring" strategy, as it exploits a powerful technique to capture a large set of solutions for any new SAT counter-example. The overall method is completed with a branch-and-bound heuristic which evaluates lower and upper bounds of the schedule length, to reduce the state space that has to be visited. Our results show that the proposed strategy significantly improves the blind binate covering schema, and it outperforms general purpose state-of-the-art tool