Index to NASA Tech Briefs, January - June 1966

Index to NASA technological innovations for January-June 196

Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator

Powder metallurgical materials and processes for soft magnetic applications

For many designers of electrical machines, the term “soft magnetic materials” automatically means laminated electrical sheet. This is unfortunate, since for many applications, particularly at low frequencies, laminated sheet is rarely the best material choice. Soft magnetic powder materials are available to satisfy the needs of virtually any application imaginable, from plain iron, giving good induction for DC applications, to ultra-high permeability nickel irons. The use of these materials brings with it all the attendant advantages of powder metallurgical (PM) production: low cost, tight tolerances, complicated forms, and minimal material waste. For high frequency applications, a range of soft magnetic composite materials or SMCs are available which can provide magnetic performance comparable to or surpassing that of laminated sheets, while at the same time allowing much greater freedom to the designer due to their isotropic nature, which permits the implementation of complicated 3D flux paths. This paper presents a review of the available powder-based soft magnetic materials, together with typical applications and a consideration of some of the factors which must be taken into account when producing powder-based components for magnetic applications

Integrated Power/Attitude Control System (IPACS) study. Volume 2: Conceptual designs

For abstract, see N74-22706

Low-Power Energy Efficient Circuit Techniques for Small IoT Systems

Although the improvement in circuit speed has been limited in recent years, there has been increased focus on the internet of things (IoT) as technology scaling has decreased circuit size, power usage and cost. This trend has led to the development of many small sensor systems with affordable costs and diverse functions, offering people convenient connection with and control over their surroundings. This dissertation discusses the major challenges and their solutions in realizing small IoT systems, focusing on non-digital blocks, such as power converters and analog sensing blocks, which have difficulty in following the traditional scaling trends of digital circuits. To accommodate the limited energy storage and harvesting capacity of small IoT systems, this dissertation presents an energy harvester and voltage regulators with low quiescent power and good efficiency in ultra-low power ranges. Switched-capacitor-based converters with wide-range energy-efficient voltage-controlled oscillators assisted by power-efficient self-oscillating voltage doublers and new cascaded converter topologies for more conversion ratio configurability achieve efficient power conversion down to several nanowatts. To further improve the power efficiency of these systems, analog circuits essential to most wireless IoT systems are also discussed and improved. A capacitance-to-digital sensor interface and a clocked comparator design are improved by their digital-like implementation and operation in phase and frequency domain. Thanks to the removal of large passive elements and complex analog blocks, both designs achieve excellent area reduction while maintaining state-of-art energy efficiencies. Finally, a technique for removing dynamic voltage and temperature variations is presented as smaller circuits in advanced technologies are more vulnerable to these variations. A 2-D simultaneous feedback control using an on-chip oven control locks the supply voltage and temperature of a small on-chip domain and protects circuits in this locked domain from external voltage and temperature changes, demonstrating 0.0066 V/V and 0.013 °C/°C sensitivities to external changes. Simple digital implementation of the sensors and most parts of the control loops allows robust operation within wide voltage and temperature ranges.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138743/1/wanyeong_1.pd

Ultrafast and low-energy switching in voltage-controlled elliptical pMTJ

Switching magnetization in a perpendicular magnetic tunnel junction (pMTJ) via voltage controlled magnetic anisotropy (VCMA) has shown the potential to markedly reduce the switching energy. However, the requirement of an external magnetic field poses a critical bottleneck for its practical applications. In this work, we propose an elliptical-shaped pMTJ to eliminate the requirement of providing an external field by an additional circuit. We demonstrate that a 10 nm thick in-plane magnetized bias layer (BL) separated by a metallic spacer of 3 nm from the free layer (FL) can be engineered within the MTJ stack to provide the 50 mT bias magnetic field for switching. By conducting macrospin simulation, we find that a fast switching in 0.38 ns with energy consumption as low as 0.3 fJ at a voltage of 1.6 V can be achieved. Furthermore, we study the phase diagram of switching probability, showing that a pulse duration margin of 0.15 ns is obtained and a low-voltage operation (~ 1 V) is favored. Finally, the MTJ scalability is considered, and it is found that scaling-down may not be appealing in terms of both the energy consumption and the switching time for the precession based VCMA switching.Comment: There are 28 pages and 5 figure

Wireless Telemetry System for Implantable Sensors

Advanced testing of medical treatments involves experimentation on small laboratory animals, such as genetically modified mice. These subjects are used to help researchers develop medication and cures for humans. To understand the effects of the treatments, innovative telemetry systems are developed, that enable remote real-time cardiac monitoring. The latest research in the field of cardiac monitoring has revealed two major limitations with wireless implantable systems: a) the current size of implantable electronics limits the physical size of the system to larger subjects; and b) the systems only interface with one sensor type (e.g., pressure sensor only). This research focuses on the design of a wireless telemetry system architecture, intended to retrieve blood pressure and volume data. A physical prototype is created that is 2.475 cm3 and weights 4.01 g. This thesis will enable a path towards miniaturization, leading to the incorporation of a wireless system into small laboratory animals