96 research outputs found
Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects
Siirretty Doriast
High Frequency DC/DC Boost Converter
The goal of this work was to design and test a functional proof of concept of a high frequency DC to DC boost converter. The scope of this work included the design, simulation, part selection, PCB layout, fabrication, and testing of the three major design blocks. The design uses a closed loop error amplifier circuit, a power stage, and a ramp waveform generator circuit. The switching frequency will be adjustable, with a maximum goal of 20MHz
CMOS SPAD-based image sensor for single photon counting and time of flight imaging
The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised
electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and
temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon
sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology
offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high
sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with
significantly lower cost and comparable performance in low light or high speed scenarios. For example, with
temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be
formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can
yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the
entanglement of photons may be realised.
The goal of this research project is the development of such an image sensor by exploiting single photon
avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology.
SPADs have three key combined advantages over other imaging technologies: single photon sensitivity,
picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue
techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A
SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or
fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that
makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are
captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an
equivalent of 0.06 electrons.
The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast
readout and oversampled image formation are projected towards the formation of binary single photon imagers
or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to
the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error
rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image
sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film.
Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm
precision in a 60cm range
A SigmaDelta modulator for digital hearing instruments using 0.18 mum CMOS technology.
This thesis develops the design methodology for a low-voltage low-power SigmaDelta Modulator, realized using a switched op-amp technique that can be used in a hearing instrument. Switched op-amp implementation allows scaling down the design to the latest CMOS technology. A single-loop second-order SigmaDelta Modulator topology is chosen. The modulator circuit features reduced complexity, area reduction and low conversion energy. The modulator has a sampling rate of 8.2 MHz with an over-sampling ratio (OSR) of 256 to provide an audio bandwidth of 16 kHz. The modulator is implemented in a 0.18 mum digital CMOS technology with metal-to-metal sandwich structure capacitors. The modulator operates with a supply voltage of 1.8 V. The active area is 0.403 mm2. The modulator achieves a 98 dB signal-to-noise-and-distortion ratio (SNDR) and a 100 dB dynamic range (DR) at a Nyquist conversion rate of 32 kHz and consumes 1321 muW with a joule/conversion figure of merit equal to 161 x 10-12 J/s. The design methodology is developed through the extensive use of simulation tools. The behaviour simulation is carried out using Matlab/SIMULINK while circuits are simulated with Hspice using the Cadence design tools. Full-custom layout for the analog and the digital circuits is performed using the Cadence design tool. Post-processing simulation of the extracted modulator with parasitic verifies that results meet the requirements. The design has been sent to CMC for fabrication. Source: Masters Abstracts International, Volume: 43-03, page: 0947. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004
Integrated Circuits/Microchips
With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications
Analog and mixed-signal circuitry for system-assisted high-speed I/O links
The state-of-the-art design methodology for high-speed I/O links is to specify component-level design requirements to achieve high-fidelity component-level performance. While designing each component in the link with high fidelity guarantees a reliable link, it does not inherently optimize the link for metrics such as the power, design complexity, or bit error rate performance. Recently, due to the increased demand for data bandwidth in backplane I/O, a system-assisted design methodology has been developed to optimize the system for a given set of metrics. By optimizing on the system level rather than the component level, the performance at the component level can be reduced from high quality to sufficient when the component is deployed within the I/O link. The new system-level design methodology encourages the utilization of novel circuit architectures. In this dissertation, novel analog and mixed-signal circuitry for system-assisted high-speed I/O links is presented. The novel circuitry expands upon traditional analog and mixed-signal circuit architectures in order to achieve system-level design goals and requirements without significant power or area overhead
Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations
Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts.
The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2.
An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology.
Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies
Asynchrobatic logic for low-power VLSI design
In this work, Asynchrobatic Logic is presented. It is a novel low-power
design style that combines the energy saving benefits of asynchronous logic
and adiabatic logic to produce systems whose power dissipation is reduced in
several different ways. The term “Asynchrobatic” is a new word that can be
used to describe these types of systems, and is derived from the
concatenation and shortening of Asynchronous, Adiabatic Logic. This thesis
introduces the concept and theory behind Asynchrobatic Logic. It first
provides an introductory background to both underlying parent technologies
(asynchronous logic and adiabatic logic). The background material continues
with an explanation of a number of possible methods for designing complex
data-path cells used in the adiabatic data-path. Asynchrobatic Logic is then
introduced as a comparison between asynchronous and Asynchrobatic buffer
chains, showing that for wide systems, it operates more efficiently. Two
more-complex sub-systems are presented, firstly a layout implementation of
the substitution boxes from the Twofish encryption algorithm, and secondly a
front-end only (without parasitic capacitances, resistances) simulation that
demonstrates a functional system capable of calculating the Greatest
Common Denominator (GCD) of a pair of 16-bit unsigned integers, which
under typical conditions on a 0.35μm process, executed a test vector requiring
twenty-four iterations in 2.067μs with a power consumption of 3.257nW.
These examples show that the concept of Asynchrobatic Logic has the
potential to be used in real-world applications, and is not just theory without
application. At the time of its first publication in 2004, Asynchrobatic Logic
was both unique and ground-breaking, as this was the first time that
consideration had been given to operating large-scale adiabatic logic in an
asynchronous fashion, and the first time that Asynchronous Stepwise
Charging (ASWC) had been used to drive an adiabatic data-path
Recommended from our members
Energy efficient communication across on-chip wires in digital CMOS
For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have increased. Wires routed for non-local communication now consume a large and increasing portion of the power, thermal and area budgets in CMOS designs. Additionally, dynamic energy expended in driving locally routed wires has become comparable to that expended in logic. The goal of this research is to investigate methods of reducing the energy required for on-chip communication, primarily through the use of low-voltage swing signaling. A network-on-chip routing architecture is presented that uses complementary architectural and low-voltage swing signaling techniques to significantly improve the latency, throughput and power of an on-chip network. On-chip signaling circuits are presented that improve the suitability of low-voltage swing signaling for short wire lengths and reduced supply voltages. Finally, a procedure for improving the energy efficiency of wire loads in digital CMOS through the automated insertion of low-voltage swing signaling circuits is presented
Disseny microelectrnic de circuits discriminadors de polsos pel detector LHCb
The aim of this thesis is to present a solution for implementing the front end system of the Scintillator Pad Detector (SPD) of the calorimeter system of the LHCb experiment that will start in 2008 at the Large Hadron Collider (LHC) at CERN. The requirements of this specific system are discussed and an integrated solution is presented, both at system and circuit level. We also report some methodological achievements. In first place, a method to study the PSRR (and any transfer function) in fully differential circuits taking into account the effect of parameter mismatch is proposed. Concerning noise analysis, a method to study time variant circuits in the frequency domain is presented and justified. This would open the possibility to study the effect of 1/f noise in time variants circuits. In addition, it will be shown that the architecture developed for this system is a general solution for front ends in high luminosity experiments that must be operated with no dead time and must be robust against ballistic deficit
- …