High Capacity and Automatic Functional Extraction Tool for Industrial VLSI Circuit Designs Abstract

In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV-Extract and is part of a comprehensive Formal Equivalence Verification (FEV) system developed at Intel to verify modern microprocessor designs. FEV-Extract employs a powerful hierarchical analysis procedure, and advanced and generic algorithms for automatic recognition of logical primitives, to cope with variety of circuit design styles and their complexity. Logic equations are then extracted to generate a behavioral RTL model described in industrial standard HDL languages, to be used in the formal equivalence verification, logic simulation, synthesis and testability flows. Categories and Subject Descriptors D.3 [VERIFICATION, MODELING AND SIMULATION]: Formal verification techniques. Switch, logic and high-level simulation, design validation, HW/SW co-simulation, combinational and sequential equivalence checking. Model checking. Theorem proving