Power and memory optimization techniques in embedded systems design

Embedded systems incur tight constraints on power consumption and memory (which impacts size) in addition to other constraints such as weight and cost. This dissertation addresses two key factors in embedded system design, namely minimization of power consumption and memory requirement. The first part of this dissertation considers the problem of optimizing power consumption (peak power as well as average power) in high-level synthesis (HLS). The second part deals with memory usage optimization mainly targeting a restricted class of computations expressed as loops accessing large data arrays that arises in scientific computing such as the coupled cluster and configuration interaction methods in quantum chemistry. First, a mixed-integer linear programming (MILP) formulation is presented for the scheduling problem in HLS using multiple supply-voltages in order to optimize peak power as well as average power and energy consumptions. For large designs, the MILP formulation may not be suitable; therefore, a two-phase iterative linear programming formulation and a power-resource-saving heuristic are presented to solve this problem. In addition, a new heuristic that uses an adaptation of the well-known force-directed scheduling heuristic is presented for the same problem. Next, this work considers the problem of module selection simultaneously with scheduling for minimizing peak and average power consumption. Then, the problem of power consumption (peak and average) in synchronous sequential designs is addressed. A solution integrating basic retiming and multiple-voltage scheduling (MVS) is proposed and evaluated. A two-stage algorithm namely power-oriented retiming followed by a MVS technique for peak and/or average power optimization is presented. Memory optimization is addressed next. Dynamic memory usage optimization during the evaluation of a special class of interdependent large data arrays is considered. Finally, this dissertation develops a novel integer-linear programming (ILP) formulation for static memory optimization using the well-known fusion technique by encoding of legality rules for loop fusion of a special class of loops using logical constraints over binary decision variables and a highly effective approximation of memory usage

Block level voltage

Over the past years, state-of-art power optimization methods move towards higher abstraction levels that result in more efficient power savings. Among existing power optimization approaches, dynamic power management (DPM) is considered to be one of the most effective strategies. Depending on abstraction levels, DPM can be implemented in different formats but here we focus on scheduling that is more suitable for real-time system design use. This differs from the concurrent scheduling approaches that start from either the HLS (High-Level Synthesis) or RTS (Real-Time System) point of view, we propose a synergy solution of both approaches, namely block-level voltage/frequency scheduling (BLVFS). The presented block-level voltage/ frequency scheduling approach shows a generic solution for low power SoC (System on Chip) system design while the approaches which belong to the HLS and RTS categories have a strong dependency on the system functionalities. Consider a SoC as a combination of heterogeneous functional blocks, our approach provides efficient power savings by dynamically scheduling the scaling of voltage and frequency at the same time. Simulation results indicate that by using heuristic based strategies significant power savings can be achieved

Enhancing Power Efficient Design Techniques in Deep Submicron Era

Excessive power dissipation has been one of the major bottlenecks for design and manufacture in the past couple of decades. Power efficient design has become more and more challenging when technology scales down to the deep submicron era that features the dominance of leakage, the manufacture variation, the on-chip temperature variation and higher reliability requirements, among others. Most of the computer aided design (CAD) tools and algorithms currently used in industry were developed in the pre deep submicron era and did not consider the new features explicitly and adequately. Recent research advances in deep submicron design, such as the mechanisms of leakage, the source and characterization of manufacture variation, the cause and models of on-chip temperature variation, provide us the opportunity to incorporate these important issues in power efficient design. We explore this opportunity in this dissertation by demonstrating that significant power reduction can be achieved with only minor modification to the existing CAD tools and algorithms. First, we consider peak current, which has become critical for circuit's reliability in deep submicron design. Traditional low power design techniques focus on the reduction of average power. We propose to reduce peak current while keeping the overhead on average power as small as possible. Second, dual Vt technique and gate sizing have been used simultaneously for leakage savings. However, this approach becomes less effective in deep submicron design. We propose to use the newly developed process-induced mechanical stress to enhance its performance. Finally, in deep submicron design, the impact of on-chip temperature variation on leakage and performance becomes more and more significant. We propose a temperature-aware dual Vt approach to alleviate hot spots and achieve further leakage reduction. We also consider this leakage-temperature dependency in the dynamic voltage scaling approach and discover that a commonly accepted result is incorrect for the current technology. We conduct extensive experiments with popular design benchmarks, using the latest industry CAD tools and design libraries. The results show that our proposed enhancements are promising in power saving and are practical to solve the low power design challenges in deep submicron era

Input current shaped ac-to-dc converters

Input current shaping techniques for ac-to-dc converters were investigated. Input frequencies much higher than normal, up to 20 kHz were emphasized. Several methods of shaping the input current waveform in ac-to-dc converters were reviewed. The simplest method is the LC filter following the rectifier. The next simplest method is the resistor emulation approach in which the inductor size is determined by the converter switching frequency and not by the line input frequency. Other methods require complicated switch drive algorithms to construct the input current waveshape. For a high-frequency line input, on the order of 20 kHz, the simple LC cannot be discarded so peremptorily, since the inductor size can be compared with that for the resistor emulation method. In fact, since a dc regulator will normally be required after the filter anyway, the total component count is almost the same as for the resistor emulation method, in which the filter is effectively incorporated into the regulator

Low Power system Design techniques for mobile computers

Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: min imizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system, including error control, sys tem decomposition, communication and MAC protocols, and low power short range net works

Development of a multilevel converter topology for transformer-less connection of renewable energy systems

The global need to reduce dependence on fossil fuels for electricity production has become an ongoing research theme in the last decade. Clean energy sources (such as wind energy and solar energy) have considerable potential to reduce reliance on fossil fuels and mitigate climate change. However, wind energy is going to become more mainstream due to technological advancement and geographical availability. Therefore, various technologies exist to maximize the inherent advantages of using wind energy conversion systems (WECSs) to generate electrical power. One important technology is the power electronics interface that enables the transfer and effective control of electrical power from the renewable energy source to the grid through the filter and isolation transformer. However, the transformer is bulky, generates losses, and is also very costly. Therefore, the term "transformer-less connection" refers to eliminating a step-up transformer from the WECS, while the power conversion stage performs the conventional functions of a transformer. Existing power converter configurations for transformer-less connection of a WECS are either based on the generator-converter configuration or three-stage power converter configuration. These configurations consist of conventional multilevel converter topologies and two-stage power conversion between the generator-side converter topology and the high-order filter connected to the collection point of the wind power plant (WPP). Thus, the complexity and cost of these existing configurations are significant at higher voltage and power ratings. Therefore, a single-stage multilevel converter topology is proposed to simplify the power conversion stage of a transformer-less WECS. Furthermore, the primary design challenges – such as multiple clamping devices, multiple dc-link capacitors, and series-connected power semiconductor devices – have been mitigated by the proposed converter topology. The proposed converter topology, known as the "tapped inductor quasi-Z-source nested neutral-point-clamped (NNPC) converter," has been analyzed, and designed, and a prototype of the topology developed for experimental verification. A field-programmable gate array (FPGA)-based modulation technique and voltage balancing control technique for maintaining the clamping capacitor voltages was developed. Hence, the proposed converter topology presents a single-stage power conversion configuration. Efficiency analysis of the proposed converter topology has been studied and compared to the intermediate and grid-side converter topology of a three-stage power converter configuration. A direct current (DC) component minimization technique to minimize the dc component generated by the proposed converter topology was investigated, developed, and verified experimentally. The proposed dc component minimization technique consists of a sensing and measurement circuitry with a digital notch filter. This thesis presents a detailed and comprehensive overview of the existing power converter configurations developed for transformer-less WECS applications. Based on the developed 2 comparative benchmark factor (CBF), the merits and demerits of each power converter configuration in terms of the component counts and grid compliance have been presented. In terms of cost comparison, the three-stage power converter configuration is more cost-effective than the generatorconverter configuration. Furthermore, the cost-benefit analysis of deploying a transformer-less WECSs in a WPP is evaluated and compared with conventional WECS in a WPP based on power converter configurations and collection system. Overall, the total cost of the collection system of WPP with transformer-less WECSs is about 23% less than the total cost of WPP with conventional WECs. The derivation and theoretical analysis of the proposed five-level tapped inductor quasi-Z-source NNPC converter topology have been presented, emphasizing its operating principles, steady-state analysis, and deriving equations to calculate its inductance and capacitance values. Furthermore, the FPGA implementation of the proposed converter topology was verified experimentally with a developed prototype of the topology. The efficiency of the proposed converter topology has been evaluated by varying the switching frequency and loads. Furthermore, the proposed converter topology is more efficient than the five-level DC-DC converter with a five-level diode-clamped converter (DCC) topology under the three-stage power converter configuration. Also, the cost analysis of the proposed converter topology and the conventional converter topology shows that it is more economical to deploy the proposed converter topology at the grid side of a transformer-less WECS

Modeling and Analysis of Power Processing Systems

The feasibility of formulating a methodology for the modeling and analysis of aerospace electrical power processing systems is investigated. It is shown that a digital computer may be used in an interactive mode for the design, modeling, analysis, and comparison of power processing systems

Cascade multilevel inverters for large hybrid-electric vehicle applications with variant DC sources

This thesis investigates using the cascade multilevel inverter as an alternative to conventional pulse width modulated inverters for large hybrid-electric vehicle (HEV) drivetrain applications. Previous research considered constant and equal dc sources with invariant behavior; however, this research extends earlier work to include variant dc sources, which are typical of lead-acid batteries when used in HEVs. This thesis also investigates methods to minimize the total harmonic distortion of the synthesized multilevel waveform and to help balance the battery voltage. The harmonic elimination method was used to eliminate selected lower dominant harmonics resulting from the inverter switching action. Switching points (angles) were determined using an iterative technique to solve the system of nonlinear transcendental equations. The total harmonic distortion was investigated over a wide range of possible output control voltages and number of voltage levels used to synthesize the output waveform. As expected, the line-to-line voltage of the three-phase multilevel inverter\u27s voltage was observed to be zero when used with an ideal low-pass filter; however, the total harmonic distortion increased significantly for both the phase- and line-voltages as the number of synthesis voltage levels decreased. Also, a switching pattern that would help balance and equalize the individual battery voltages within an HEV battery pack was developed. The individual batteries with the higher voltages would be assigned the longer duty cycle, and the batteries with the lower voltages would be skipped or assigned the lower duty cycles