High Level Modeling for Parallel Executions of Nested Loop Algorithms

High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications (algorithms) and the implementations (architecture), a mapping of the former into the latter, and a simulator for fast execution of the whole. Signal processing algorithms are very often nested-loop algorithms with a high degree of inherent parallelism. This paper presents - for such applications - suitable application and implemetation models, a method to convert a given imperative executable specification to a specification in terms of the applicationmodel, a method to map this specification into an architecture specification in terms of the implementationmodel, and a method to analyze the performance through simulation. The methods and tools are illustrated by means of an example