459 research outputs found
Redesigning OP2 Compiler to Use HPX Runtime Asynchronous Techniques
Maximizing parallelism level in applications can be achieved by minimizing
overheads due to load imbalances and waiting time due to memory latencies.
Compiler optimization is one of the most effective solutions to tackle this
problem. The compiler is able to detect the data dependencies in an application
and is able to analyze the specific sections of code for parallelization
potential. However, all of these techniques provided with a compiler are
usually applied at compile time, so they rely on static analysis, which is
insufficient for achieving maximum parallelism and producing desired
application scalability. One solution to address this challenge is the use of
runtime methods. This strategy can be implemented by delaying certain amount of
code analysis to be done at runtime. In this research, we improve the parallel
application performance generated by the OP2 compiler by leveraging HPX, a C++
runtime system, to provide runtime optimizations. These optimizations include
asynchronous tasking, loop interleaving, dynamic chunk sizing, and data
prefetching. The results of the research were evaluated using an Airfoil
application which showed a 40-50% improvement in parallel performance.Comment: 18th IEEE International Workshop on Parallel and Distributed
Scientific and Engineering Computing (PDSEC 2017
Multithreading Aware Hardware Prefetching for Chip Multiprocessors
To take advantage of the processing power in the Chip Multiprocessors design,
applications must be divided into semi-independent processes that can run concur-
rently on multiple cores within a system. Therefore, programmers must insert thread
synchronization semantics (i.e. locks, barriers, and condition variables) to synchro-
nize data access between processes. Indeed, threads spend long time waiting to
acquire the lock of a critical section. In addition, a processor has to stall execution
to wait for load data accesses to complete. Furthermore, there are often independent instructions which include load instructions beyond synchronization semantics that could be executed in parallel while a thread waits on the synchronization semantics. The conveniences of the cache memories come with some extra cost in Chip Multiprocessors. Cache Coherence mechanisms address the Memory Consistency problem. However, Cache Coherence adds considerable overhead to memory accesses. Having aggressive prefetcher on different cores of a Chip Multiprocessor can definitely lead to significant system performance degradation when running multi-threaded applications. This result of prefetch-demand interference when a prefetcher in one core ends up pulling shared data from a producing core before it has been written, the cache block will end up transitioning back and forth between the cores and result in useless prefetch, saturating the memory bandwidth and substantially increase the latency to critical shared data.
We present a hardware prefetcher that enables large performance improvements
from prefetching in Chip Multiprocessors by significantly reducing prefetch-demand
interference. Furthermore, it will utilize the time that a thread spends waiting on syn-
chronization semantics to run ahead of the critical section to speculate and prefetch independent load instruction data beyond the synchronization semantics
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Graph prefetching using data structure knowledge
Searches on large graphs are heavily memory latency bound,
as a result of many high latency DRAM accesses. Due to
the highly irregular nature of the access patterns involved,
caches and prefetchers, both hardware and software, perform
poorly on graph workloads. This leads to CPU stalling for
the majority of the time. However, in many cases the data
access pattern is well defined and predictable in advance,
many falling into a small set of simple patterns. Although
existing implicit prefetchers cannot bring significant benefit,
a prefetcher armed with knowledge of the data structures
and access patterns could accurately anticipate applications'
traversals to bring in the appropriate data.
This paper presents a design of an explicitly configured
prefetcher to improve performance for breadth-first searches
and sequential iteration on the efficient and commonly-used
compressed sparse row graph format. By snooping L1 cache
accesses from the core and reacting to data returned from its
own prefetches, the prefetcher can schedule timely loads of
data in advance of the application needing it. For a range of
applications and graph sizes, our prefetcher achieves average
speedups of 2.3x, and up to 3.3x, with little impact on
memory bandwidth requirements.This work was supported by the Engineering and Physical
Sciences Research Council (EPSRC), through grant references EP/K026399/1 and EP/M506485/1, and ARM Ltd.This is the author accepted manuscript. The final version is available from ACM at http://dx.doi.org/10.1145/2925426.2926254
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