Hardware-Software Codesign for Dynamically Reconfigurable Architectures

. The paper addresses the problem of mapping an application specified as a task graph on a heterogeneous architecture which contains a software processor, a dynamically reconfigurable hardware coprocessor and memory elements. The problem comprises of three subproblems: partitioning of tasks between hardware and software, assigning tasks mapped on hardware to different temporal segments and scheduling task execution, reconfiguration of hardware, inter-processor and intraprocessor communication. We present a heuristic based technique for solving the problem. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm and experimentation with synthetic graphs. 1 Introduction Embedded systems typically have heterogeneous architectures which contain both off the shelf software (SW) processors and custom application specific integrated circuits (ASICs) as hardware (HW) coprocessors. The SW processors provide flexibility and help in r..