Design methodology for embedded computer vision systems

Computer vision has emerged as one of the most popular domains of embedded appli¬cations. Though various new powerful embedded platforms to support such applica¬tions have emerged in recent years, there is a distinct lack of efficient domain-specific synthesis techniques for optimized implementation of such systems. In this thesis, four different aspects that contribute to efficient design and synthesis of such systems are explored: (1) Graph Transformations: Dataflow modeling is widely used in digital signal processing (DSP) systems. However, support for dynamic behavior in such systems exists mainly at the modeling level and there is a lack of optimized synthesis tech¬niques for these models. New transformation techniques for efficient system-on-chip (SoC) design methods are proposed and implemented for cyclo-static dataflow and its parameterized version (parameterized cyclo-static dataflow) -- two powerful models that allow dynamic reconfigurability and phased behavior in DSP systems. (2) Design Space Exploration: The broad range of target platforms along with the complexity of applications provides a vast design space, calling for efficient tools to explore this space and produce effective design choices. A novel architectural level design methodology based on a formalism called multirate synchronization graphs is presented along with methods for performance evaluation. (3) Multiprocessor Communication Interface: Efficient code synthesis for emerg¬ing new parallel architectures is an important and sparsely-explored problem. A widely-encountered problem in this regard is efficient communication between pro¬cessors running different sub-systems. A widely used tool in the domain of general-purpose multiprocessor clusters is MPI (Message Passing Interface). However, this does not scale well for embedded DSP systems. A new, powerful and highly optimized communication interface for multiprocessor signal processing systems is presented in this work that is based on the integration of relevant properties of MPI with dataflow semantics. (4) Parameterized Design Framework for Particle Filters: Particle filter systems constitute an important class of applications used in a wide number of fields. An effi¬cient design and implementation framework for such systems has been implemented based on the observation that a large number of such applications exhibit similar prop¬erties. The key properties of such applications are identified and parameterized appro¬priately to realize different systems that represent useful trade-off points in the space of possible implementations

Hardware mechanisms for efficient interprocessor communication

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (p. 131-137).by Dana S. Henry.Ph.D

Hardware Mechanisms for Efficient Interprocessor Communication

Simple hardware mechanisms can speed up interprocessor communication dramatically for off-the-shelf processors. This dissertation addresses the problem of efficient interprocessor communication using a framework consisting of a user-level network interface and fast userlevel interrupts. The network interface allows fast receiving, processing, and sending of messages, while fast interrupts reduce the cost of detecting communication events such as a message arrival or an access to non-local memory. The network interface can provide a major performance boost with no modifications to the processor itself. Our network interface (NI) is user level rather than kernel level, allowing messages to be handled without operating-system interactions. The NI is registeroriented rather than FIFO oriented, allowing the various elements of a message to be read and written in an arbitrary order. The NI provides enhancements for common operations such as dispatching on, replying to,and forwarding of messa..