Hardware Scheduling in High-Speed, High-Capacity IP Routers

The key to the design of high speed, high capacity IP switches/routers with multiple servers in an input/output module is a fast scheduling scheme resolving input and output contentions. Such a scheduling scheme is a typical application of the multirequester, multi-server (MRMS) problem. To efficiently solve the MRMS problem and provide fair services to all requesters, we introduce four programmable k-selectors designs in this paper. Simulations on Altera’s CPLD (FPGA) demonstrate that our designs achieve significant performance improvement over the design using programmable priority encoders. Programmable k-selectors are very useful to construct hardware Request-Grant or Request-Grant-Accept schedulers for high-speed, high-capacity multi-server switches/routers