VHDL Implementation of Hybrid Block Cipher Method (SRC)

This paper discusses the hardware design of the hybrid block cipher methodthat combines the RC6 cipher and the Serpent cipher.The block size is 128 bits, and the key can be any length up to 256 bytes. Thisalgorithm is designed to take advantage of the powerful, which is supported byRC6 and Serpent encryption algorithms with overcoming their weaknesses,resulting in a much improved security/performance tradeoff over existing ciphers.The discussion addresses hardware design and VHDL implementation of the keyexpansion algorithm and the encryption algorithm