2 research outputs found

    HTCC: Haskell to Handel-C Compiler

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    Functional programming languages, such as Haskell, enable simple, concise, and correct-by-construction hardware development. HTCC compiles a subset of Haskell to Handel-C language with hardware output. Moreover, HTCC generates VHDL, Verilog, EDIF, and SystemC programs. The design of HTCC compiler includes lexical, syntax and semantic analyzers. HTCC automates a transformational derivation methodology to rapidly produce hardware that maps onto Field Programmable Gate Arrays (FPGAs) . HTCC is generated using ANTLR compiler-compiler tool and supports an effective integrated development environment. This paper presents the design rationale and the implementation of HTCC. Several sample generations of first-class and higher-order functions are presented. In-addition, a compilation case-study is presented for the XTEA cipher. The investigation comprises a thorough evaluation and performance analysis. The targeted FPGAs include Cyclone II, Stratix IV, and Virtex-6 from Altera and Xilinx.Comment: 8 pages, 8 figures, 2 table

    Hardware synthesis of a parallel JPEG decoder from its functional specification

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    Abstract Given the recent emergence of cheap reconfigurable hardware, such as the FPGA, it is now possible to obtain reconfigurable circuits with upwards of one hundred million gates. Although we have such enormously powerful hardware at our fingertips, we are still somewhat lacking in techniques to properly exploit this technology to its full potential. We propose a development strategy commencing with a clear, intuitive and provably correct specification in a functional language such as Haskell. We then take this specification, and, applying a set of formal transformation laws, refine it into a behavioural definition in Handel-C, exposing the implicit parallelism along the way. This definition can then be compiled onto an FPGA. We apply this technique to a non-trivial, real world problem- a JPEG decompression algorithm, and achieve a truly scalable, parallel hardware implementation. 1
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