GraphML-Based Exploration and Evaluation of Efficient Parallelization Alternatives for Automation Firmware

Graphs are an accepted and popular way of representing and solving problems of various kinds. Thus, applications of graphs as well as related topics such as graph visualization and graph representation are numerous. Our application is located in the domain of industrial automation and driven by the need of parallelizing our controller's firmware for the upcoming multi-core CPUs. As efficiency matters, we thereby aim at gaining maximum performance increases by spending no more implementation effort than necessary. In order to achieve that objective, we at first want to explore, evaluate and visualize those efficient parallelization alternatives by means of a graph-based model of our firmware. Thus, we are currently developing the EEEPA ( Exploration and E valuation of Efficient Parallelization Alternatives) tool for this purpose. Thereby, we have chosen and extended GraphML 1, a widespread format for graph representation