Generating Efficient Tests for Continuous Scan

傳統的 scan-based 電路設計花費了很多的測試時間在測試向量的輸入和結果的輸出上，所以測試成本提高了很多。在這篇論文裡，我們提出在結構上做些改變的 scan-based 電路設計，這個電路設計可以在每個 clock cycle 作一次測試。當有適當測試向量時，這種經過改變的 scan-based 電路設計將可很明顯的減少測試的時間。在這樣的測試環境下，我們發展了一些可產生高效率測試向量的演算法，並且將這演算法運用到我們提出的測試方法中對一些 ISCAS Benchmark 電路作測試實驗。結果顯示，我們提出的測試方式只需要約原來傳統 scan-based 電路設計 10%-30% 的 clock cycle 就可達到同樣高的錯誤涵蓋率。Conventional scan-based designs spend a lot of testing time in shifting test patterns and output responses, which greatly increases the testing cost. In this thesis, we propose a modified structure for scan-based design in which a test is conducted in every clock cycle. This approach may significantly reduce the test application time when appropriate test vectors are applied. We develop algorithms to generate efficient test input for the test environment, and conduct experiments on our methods with ISCAS benchmark circuits. The results show that we can achieve high fault coverage with only about 10%-30% of the clock cycles required in conventional scan-based design.第一章 簡介………………………………………………………………1 1.1 研究動機…………………………………………………………1 1.2 研究目標…………………………………………………………4 第二章 背景知識…………………………………………………………6 2.1 Scan based 測試環境(Scan based test environment) ...6 2.2 MISR (Multiple-Input Signature Registers).......10 2.3 針對scan-based 測試環境作最佳化的研究 ………………….16 2.3.1 經由測試輸入端的改變來減少scan shift 的動作……..17 2.3.2 多個模組經由測試輸入端的共享來減少scan shift 的動作 …………………………………………………….19 2.3.3 利用輸出與輸入做的 scan shift 次數的不同來減 少整體測試時間…………………………………………..22 2.3.4 利用倆連續的測試向量的關係來減少 scan shift 的動作 …………………………………………………….24 第三章 Continuous Scan ………………………………………………..25 第四章 測試串列的產生與最佳化的演算法……………………………30 4.1 用 Deterministic vectors 的向量壓縮 ……………………….31 4.2 壓縮演算法一 ………………………………………………….34 4.3 壓縮演算法二 …………………………………………………...38 4.4 測試產生的處理方式(Test Generation Process) ……………..40 第五章 實驗結果…………………………………………………………42 第六章 減少 MISR 的大小…………………………………………….44 第七章 結論與未來工作 ………………………………………………..49 參考文獻…………………………………………………………………..5

Generating Efficient Tests for Continuous Scan

Conventional scan-based designs spend a lot of testing time in shifting test patterns and output responses, which greatly increases the testing cost. In this paper, we propose a modified approach for scan-based design in which a test is conducted in every clock cycle. This approach may significantly reduce the test application time when appropriate test vectors are applied. We develop algorithms to generate efficient test input for the test environment, and experimental results show that we can achieve high fault coverage with only about 10%-30 % of the clock cycles required in conventional scan-based design