Liquid Transport Pipeline Monitoring Architecture Based on State Estimators for Leak Detection and Location

This research presents the implementation of optimization algorithms to build auxiliary signals that can be injected as inputs into a pipeline in order to estimate —by using state observers—physical parameters such as the friction or the velocity of sound in the fluid. For the state estimator design, the parameters to be estimated are incorporated into the state vector of a Liénard-type model of a pipeline such that the observer is constructed from the augmented model. A prescribed observability degree of the augmented model is guaranteed by optimization algorithms by building an optimal input for the identification. The minimization of the input energy is used to define the optimality of the input, whereas the observability Gramian is used to verify the observability. Besides optimization algorithms, a novel method, based on a Liénard-type model, to diagnose single and sequential leaks in pipelines is proposed. In this case, the Liénard-type model that describes the fluid behavior in a pipeline is given only in terms of the flow rate. This method was conceived to be applied in pipelines solely instrumented with flowmeters or in conjunction with pressure sensors that are temporarily out of service. The design approach starts with the discretization of the Liénard-type model spatial domain into a prescribed number of sections. Such discretization is performed to obtain a lumped model capable of providing a solution (an internal flow rate) for every section. From this lumped model, a set of algebraic equations (known as residuals) are deduced as the difference between the internal discrete flows and the nominal flow (the mean of the flow rate calculated prior to the leak). The residual closest to zero will indicate the section where a leak is occurring. The main contribution of our method is that it only requires flow measurements at the pipeline ends, which leads to cost reductions. Some simulation-based tes

Integration of Active Systems for a Global Chassis Control Design

Vehicle chassis control active systems (braking, suspension, steering and driveline), from the first ABS/ESC control unit to the current advanced driver assistance systems (ADAS), are progressively revolutionizing the way of thinking and designing the vehicle, improving its interaction with the surrounding world (V2V and V2X) and have led to excellent results in terms of safety and performances (dynamic behavior and drivability). They are usually referred as intelligent vehicles due to a software/hardware architecture able to assist the driver for achieving specific safety margin and/or optimal vehicle dynamic behavior. Moreover, industrial and academic communities agree that these technologies will progress till the diffusion of the so called autonomous cars which are able to drive robustly in a wide range of traffic scenarios. Different autonomous vehicles are already available in Europe, Japan and United States and several solutions have been proposed for smart cities and/or small public area like university campus. In this context, the present research activity aims at improving safety, comfort and performances through the integration of global active chassis control: the purposes are to study, design and implement control strategies to support the driver for achieving one or more final target among safety, comfort and performance. Specifically, the vehicle subsystems that are involved in the present research for active systems development are the steering system, the propulsion system, the transmission and the braking system. The thesis is divided into three sections related to different applications of active systems that, starting from a robust theoretical design procedure, are strongly supported by objective experimental results obtained fromHardware In the Loop (HIL) test rigs and/or proving ground testing sessions. The first chapter is dedicated to one of the most discussed topic about autonomous driving due to its impact from the social point of view and in terms of human error mitigation when the driver is not prompt enough. In particular, it is here analyzed the automated steering control which is already implemented for automatic parking and that could represent also a key element for conventional passenger car in emergency situation where a braking intervention is not enough for avoiding an imminent collision. The activity is focused on different steering controllers design and their implementation for an autonomous vehicle; an obstacle collision avoidance adaptation is introduced for future implementations. Three different controllers, Proportional Derivative (PD), PD+Feedforward (FF) e PD+Integral Sliding Mode (ISM), are designed for tracking a reference trajectory that can be modified in real-time for obstacle avoidance purposes. Furthermore, PD+FF and PD+ISM logic are able to improve the tracking performances of automated steering during cornering maneuvers, relevant fromthe collision avoidance point of view. Path tracking control and its obstacle avoidance enhancement is also shown during experimental tests executed in a proving ground through its implementation for an autonomous vehicle demonstrator. Even if the activity is presented for an autonomous vehicle, the active control can be developed also for a conventional vehicle equipped with an Electronic Power Steering (EPS) or Steer-by-wire architectures. The second chapter describes a Torque Vectoring (TV) control strategy, applied to a Fully Electric Vehicle (FEV) with four independent electric motor (one for each wheel), that aims to optimize the lateral vehicle behavior by a proper electric motor torque regulation. A yaw rate controller is presented and designed in order to achieve a desired steady-state lateral behaviour of the car (handling task). Furthermore, a sideslip angle controller is also integrated to preserve vehicle stability during emergency situations (safety task). LQR, LQR+FF and ISM strategies are formulated and explained for yaw rate and concurrent yaw rate/sideslip angle control techniques also comparing their advantages and weakness points. The TV strategy is implemented and calibrated on a FEV demonstrator by executing experimental maneuvers (step steer, skid pad, lane change and sequence of step steers) thus proving the efficacy of the proposed controller and the safety contribution guaranteed by the sideslip control. The TV could be also applied for internal combustion engine driven vehicles by installing specific torque vectoring differentials, able to distribute the torque generated by the engine to each wheel independently. The TV strategy evaluated in the second chapter can be influenced by the presence of a transmission between themotor (or the engine) and wheels (where the torque control is supposed to be designed): in addition to the mechanical delay introduced by transmission components, the presence of gears backlashes can provoke undesired noises and vibrations in presence of torque sign inversion. The last chapter is thus related to a new method for noises and vibration attenuation for a Dual Clutch Transmission (DCT). This is achieved in a new way by integrating the powertrain control with the braking system control, which are historically and conventionally analyzed and designed separately. It is showed that a torsional preload effect can be obtained on transmission components by increasing the wheel torque and concurrently applying a braking wheel torque. For this reason, a pressure following controller is presented and validated through a Hardware In the Loop (HIL) test rig in order to track a reference value of braking torque thus ensuring the desired preload effect and noises reduction. Experimental results demonstrates the efficacy of the controller, also opening new scenario for global chassis control design. Finally, some general conclusions are drawn and possible future activities and recommendations are proposed for further investigations or improvements with respect to the results shown in the present work

Energy-Efficient and Reliable Computing in Dark Silicon Era

Dark silicon denotes the phenomenon that, due to thermal and power constraints, the fraction of transistors that can operate at full frequency is decreasing in each technology generation. Moore’s law and Dennard scaling had been backed and coupled appropriately for five decades to bring commensurate exponential performance via single core and later muti-core design. However, recalculating Dennard scaling for recent small technology sizes shows that current ongoing multi-core growth is demanding exponential thermal design power to achieve linear performance increase. This process hits a power wall where raises the amount of dark or dim silicon on future multi/many-core chips more and more. Furthermore, from another perspective, by increasing the number of transistors on the area of a single chip and susceptibility to internal defects alongside aging phenomena, which also is exacerbated by high chip thermal density, monitoring and managing the chip reliability before and after its activation is becoming a necessity. The proposed approaches and experimental investigations in this thesis focus on two main tracks: 1) power awareness and 2) reliability awareness in dark silicon era, where later these two tracks will combine together. In the first track, the main goal is to increase the level of returns in terms of main important features in chip design, such as performance and throughput, while maximum power limit is honored. In fact, we show that by managing the power while having dark silicon, all the traditional benefits that could be achieved by proceeding in Moore’s law can be also achieved in the dark silicon era, however, with a lower amount. Via the track of reliability awareness in dark silicon era, we show that dark silicon can be considered as an opportunity to be exploited for different instances of benefits, namely life-time increase and online testing. We discuss how dark silicon can be exploited to guarantee the system lifetime to be above a certain target value and, furthermore, how dark silicon can be exploited to apply low cost non-intrusive online testing on the cores. After the demonstration of power and reliability awareness while having dark silicon, two approaches will be discussed as the case study where the power and reliability awareness are combined together. The first approach demonstrates how chip reliability can be used as a supplementary metric for power-reliability management. While the second approach provides a trade-off between workload performance and system reliability by simultaneously honoring the given power budget and target reliability

Time-Delay Switch Attack on Networked Control Systems, Effects and Countermeasures

In recent years, the security of networked control systems (NCSs) has been an important challenge for many researchers. Although the security schemes for networked control systems have advanced in the past several years, there have been many acknowledged cyber attacks. As a result, this dissertation proposes the use of a novel time-delay switch (TDS) attack by introducing time delays into the dynamics of NCSs. Such an attack has devastating effects on NCSs if prevention techniques and countermeasures are not considered in the design of these systems. To overcome the stability issue caused by TDS attacks, this dissertation proposes a new detector to track TDS attacks in real time. This method relies on an estimator that will estimate and track time delays introduced by a hacker. Once a detector obtains the maximum tolerable time delay of a plant’s optimal controller (for which the plant remains secure and stable), it issues an alarm signal and directs the system to its alarm state. In the alarm state, the plant operates under the control of an emergency controller that can be local or networked to the plant and remains in this stable mode until the networked control system state is restored. In another effort, this dissertation evaluates different control methods to find out which one is more stable when under a TDS attack than others. Also, a novel, simple and effective controller is proposed to thwart TDS attacks on the sensing loop (SL). The modified controller controls the system under a TDS attack. Also, the time-delay estimator will track time delays introduced by a hacker using a modified model reference-based control with an indirect supervisor and a modified least mean square (LMS) minimization technique. Furthermore, here, the demonstration proves that the cryptographic solutions are ineffective in the recovery from TDS attacks. A cryptography-free TDS recovery (CF-TDSR) communication protocol enhancement is introduced to leverage the adaptive channel redundancy techniques, along with a novel state estimator to detect and assist in the recovery of the destabilizing effects of TDS attacks. The conclusion shows how the CF-TDSR ensures the control stability of linear time invariant systems

Virtual Runtime Application Partitions for Resource Management in Massively Parallel Architectures

This thesis presents a novel design paradigm, called Virtual Runtime Application Partitions (VRAP), to judiciously utilize the on-chip resources. As the dark silicon era approaches, where the power considerations will allow only a fraction chip to be powered on, judicious resource management will become a key consideration in future designs. Most of the works on resource management treat only the physical components (i.e. computation, communication, and memory blocks) as resources and manipulate the component to application mapping to optimize various parameters (e.g. energy efficiency). To further enhance the optimization potential, in addition to the physical resources we propose to manipulate abstract resources (i.e. voltage/frequency operating point, the fault-tolerance strength, the degree of parallelism, and the configuration architecture). The proposed framework (i.e. VRAP) encapsulates methods, algorithms, and hardware blocks to provide each application with the abstract resources tailored to its needs. To test the efficacy of this concept, we have developed three distinct self adaptive environments: (i) Private Operating Environment (POE), (ii) Private Reliability Environment (PRE), and (iii) Private Configuration Environment (PCE) that collectively ensure that each application meets its deadlines using minimal platform resources. In this work several novel architectural enhancements, algorithms and policies are presented to realize the virtual runtime application partitions efficiently. Considering the future design trends, we have chosen Coarse Grained Reconfigurable Architectures (CGRAs) and Network on Chips (NoCs) to test the feasibility of our approach. Specifically, we have chosen Dynamically Reconfigurable Resource Array (DRRA) and McNoC as the representative CGRA and NoC platforms. The proposed techniques are compared and evaluated using a variety of quantitative experiments. Synthesis and simulation results demonstrate VRAP significantly enhances the energy and power efficiency compared to state of the art.Siirretty Doriast

Control and Stability of Residential Microgrid with Grid-Forming Prosumers

The rise of the prosumers (producers-consumers), residential customers equipped with behind-the-meter distributed energy resources (DER), such as battery storage and rooftop solar PV, offers an opportunity to use prosumer-owned DER innovatively. The thesis rests on the premise that prosumers equipped with grid-forming inverters can not only provide inertia to improve the frequency performance of the bulk grid but also support islanded operation of residential microgrids (low-voltage distribution feeder operated in an islanded mode), which can improve distribution grids’ resilience and reliability without purposely designing low-voltage (LV) distribution feeders as microgrids. Today, grid-following control is predominantly used to control prosumer DER, by which the prosumers behave as controlled current sources. These grid-following prosumers deliver active and reactive power by staying synchronized with the existing grid. However, they cannot operate if disconnected from the main grid due to the lack of voltage reference. This gives rise to the increasing interest in the use of grid-forming power converters, by which the prosumers behave as voltage sources. Grid-forming converters regulate their output voltage according to the reference of their own and exhibit load sharing with other prosumers even in islanded operation. Making use of grid-forming prosumers opens up opportunities to improve distribution grids’ resilience and enhance the genuine inertia of highly renewable-penetrated power systems. Firstly, electricity networks in many regional communities are prone to frequent power outages. Instead of purposely designing the community as a microgrid with dedicated grid-forming equipment, the LV feeder can be turned into a residential microgrid with multiple paralleled grid-forming prosumers. In this case, the LV feeder can operate in both grid-connected and islanded modes. Secondly, gridforming prosumers in the residential microgrid behave as voltage sources that respond naturally to the varying loads in the system. This is much like synchronous machines extracting kinetic energy from rotating masses. “Genuine” system inertia is thus enhanced, which is fundamentally different from the “emulated” inertia by fast frequency response (FFR) from grid-following converters. Against this backdrop, this thesis mainly focuses on two aspects. The first is the small-signal stability of such residential microgrids. In particular, the impact of the increasing number of grid-forming prosumers is studied based on the linearised model. The impact of the various dynamic response of primary sources is also investigated. The second is the control of the grid-forming prosumers aiming to provide sufficient inertia for the system. The control is focused on both the inverters and the DC-stage converters. Specifically, the thesis proposes an advanced controller for the DC-stage converters based on active disturbance rejection control (ADRC), which observes and rejects the “total disturbance” of the system, thereby enhancing the inertial response provided by prosumer DER. In addition, to make better use of the energy from prosumer-owned DER, an adaptive droop controller based on a piecewise power function is proposed, which ensures that residential ESS provide little power in the steady state while supplying sufficient power to cater for the demand variation during the transient state. Proposed strategies are verified by time-domain simulations

Design Space Exploration for MPSoC Architectures

Multiprocessor system-on-chip (MPSoC) designs utilize the available technology and communication architectures to meet the requirements of the upcoming applications. In MPSoC, the communication platform is both the key enabler, as well as the key differentiator for realizing efficient MPSoCs. It provides product differentiation to meet a diverse, multi-dimensional set of design constraints, including performance, power, energy, reconfigurability, scalability, cost, reliability and time-to-market. The communication resources of a single interconnection platform cannot be fully utilized by all kind of applications, such as the availability of higher communication bandwidth for computation but not data intensive applications is often unfeasible in the practical implementation. This thesis aims to perform the architecture-level design space exploration towards efficient and scalable resource utilization for MPSoC communication architecture. In order to meet the performance requirements within the design constraints, careful selection of MPSoC communication platform, resource aware partitioning and mapping of the application play important role. To enhance the utilization of communication resources, variety of techniques such as resource sharing, multicast to avoid re-transmission of identical data, and adaptive routing can be used. For implementation, these techniques should be customized according to the platform architecture. To address the resource utilization of MPSoC communication platforms, variety of architectures with different design parameters and performance levels, namely Segmented bus (SegBus), Network-on-Chip (NoC) and Three-Dimensional NoC (3D-NoC), are selected. Average packet latency and power consumption are the evaluation parameters for the proposed techniques. In conventional computing architectures, fault on a component makes the connected fault-free components inoperative. Resource sharing approach can utilize the fault-free components to retain the system performance by reducing the impact of faults. Design space exploration also guides to narrow down the selection of MPSoC architecture, which can meet the performance requirements with design constraints.Siirretty Doriast

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.Siirretty Doriast

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.Siirretty Doriast

Adaptive Knobs for Resource Efficient Computing

Performance demands of emerging domains such as artificial intelligence, machine learning and vision, Internet-of-things etc., continue to grow. Meeting such requirements on modern multi/many core systems with higher power densities, fixed power and energy budgets, and thermal constraints exacerbates the run-time management challenge. This leaves an open problem on extracting the required performance within the power and energy limits, while also ensuring thermal safety. Existing architectural solutions including asymmetric and heterogeneous cores and custom acceleration improve performance-per-watt in specific design time and static scenarios. However, satisfying applications’ performance requirements under dynamic and unknown workload scenarios subject to varying system dynamics of power, temperature and energy requires intelligent run-time management. Adaptive strategies are necessary for maximizing resource efficiency, considering i) diverse requirements and characteristics of concurrent applications, ii) dynamic workload variation, iii) core-level heterogeneity and iv) power, thermal and energy constraints. This dissertation proposes such adaptive techniques for efficient run-time resource management to maximize performance within fixed budgets under unknown and dynamic workload scenarios. Resource management strategies proposed in this dissertation comprehensively consider application and workload characteristics and variable effect of power actuation on performance for pro-active and appropriate allocation decisions. Specific contributions include i) run-time mapping approach to improve power budgets for higher throughput, ii) thermal aware performance boosting for efficient utilization of power budget and higher performance, iii) approximation as a run-time knob exploiting accuracy performance trade-offs for maximizing performance under power caps at minimal loss of accuracy and iv) co-ordinated approximation for heterogeneous systems through joint actuation of dynamic approximation and power knobs for performance guarantees with minimal power consumption. The approaches presented in this dissertation focus on adapting existing mapping techniques, performance boosting strategies, software and dynamic approximations to meet the performance requirements, simultaneously considering system constraints. The proposed strategies are compared against relevant state-of-the-art run-time management frameworks to qualitatively evaluate their efficacy