Preliminary candidate advanced avionics system for general aviation

An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered

Voyager electronic parts radiation program, volume 1

The Voyager spacecraft is subject to radiation from external natural space, from radioisotope thermoelectric generators and heater units, and from the internal environment where penetrating electrons generate surface ionization effects in semiconductor devices. Methods for radiation hardening and tests for radiation sensitivity are described. Results of characterization testing and sample screening of over 200 semiconductor devices in a radiation environment are summarized

Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods

This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness and capability of built-in-self test (BIST) implementation. It can also be generalized to the oscillation based test structures of other CMOS analog and mixed-signal integrated circuits. The practical results and simulations confirm the functionality of the proposed test method

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

Optical scanning tests of complex CMOS microcircuits

The new test method was based on the use of a raster-scanned optical stimulus in combination with special electrical test procedures. The raster-scanned optical stimulus was provided by an optical spot scanner, an instrument that combines a scanning optical microscope with electronic instrumentation to process and display the electric photoresponse signal induced in a device that is being tested

The STAR MAPS-based PiXeL detector

The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014-2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this paper

Automating defects simulation and fault modeling for SRAMs

The continues improvement in manufacturing process density for very deep sub micron technologies constantly leads to new classes of defects in memory devices. Exploring the effect of fabrication defects in future technologies, and identifying new classes of realistic functional fault models with their corresponding test sequences, is a time consuming task up to now mainly performed by hand. This paper proposes a new approach to automate this procedure. The proposed method exploits the capabilities of evolutionary algorithms to automatically identify faulty behaviors into defective memories and to define the corresponding fault models and relevant test sequences. Target defects are modeled at the electrical level in order to optimize the results to the specific technology and memory architecture

Gated multi-cycle integration (GMCI) for focal plane array (FPA) applications

In this thesis, the model and the theory of gated multi-cycle integration (GMCI) were first developed specifically for focal plane array dealing with repetitive or modulated image. The operational modes of GMCI include gated integration (GI), phase sensitive integration (PSI), multi-point summation, multi-point subtraction, multi-sample averaging and some of their combinations. Thus, the analytic theory of GMCI somehow unifies the theories of gated integration, phase sensitive detection, multiple summation and average. PSI works with background and/or dark current subtraction. As a result, the storage well of a pixel is mainly used for signal integration even if there exists a strong background. Thus, the signal-to-noise ratio, the dynamic range, the sensitivity of the detection and the noise equivalent temperature are greatly improved. For a storage well of 106 electrons, the sensitivity of the FPA operated at PSI mode could be improved by 3 orders. In addition, the transmission windows of PSI peak at odd harmonics of the modulation frequency, and therefore, the detector\u27s IN and other low frequency noise can be attenuated. A switched capacitor integrator was designed and fabricated with HP-0.5gm CMOS processing to demonstrate the feasibility of GMCI. The primary experimental results showed that the minimum detectable signal could be 5 orders less than the background, which is impossible for the conventional readout methods employed by current staring FPAs. The fixed patterns associated with switching charge injection, feedthrough, offset voltage of operational amplifier were addressed and suppressed by taking the differentia of two sampled voltages that correspond to signal integrations with 180° phase difference while keeping the same fixed pattern. GMCI, operated at PSI with multiple averages, is expected to become a powerful method in dealing with repetitive weak image swamped by strong background

Piezo-generated charge mapping revealed through Direct Piezoelectric Force Microscopy

While piezoelectrics and ferroelectrics are playing a key role in many everyday applications, there are still a number of open questions related to the physics of those materials. In order to foster the understanding of piezoelectrics and ferroelectric and pave the way to future applications, the nanoscale characterization of these materials is essential. In this light, we have developed a novel AFM based mode that obtains a direct quantitative analysis of the piezoelectric coefficient d33. This nanoscale tool is capable of detecting and reveal piezo-charge generation through the direct piezoelectric effect at the surface of the piezoelectric and ferroelectric materials. We report the first nanoscale images of the charge generated in a thick single crystal of Periodically Poled Lithium Niobate (PPLN) and a Bismuth Ferrite (BiFO3) thin film by applying a force and recording the current produced by the materials. The quantification of both d33 coefficients for PPLN and BFO are 13 +- 2 pC/N and 46 +- 7 pC/N respectively, in agreement with the values reported in the literature. This new mode can operate simultaneously with PFM mode providing a powerful tool for the electromechanical and piezo-charge generation characterization of ferroelectric and piezoelectric materials