Functional Verification of the Equator MAP1000 Microprocessor

The Advanced VLIW architecture of the Equator MAP1000 processor has many features that present significant verification challenges. We describe a functional verification methodology to address this complexity. In particular, we present an efficient method to generate directed assembly tests and a novel technique using the processor itself to control self-tests and check the results at speed using native instructions only. We also describe the use of emulation in both pre-silicon and post-silicon verification stages. 1 Introduction The complexity of modern microprocessors has grown dramatically in recent years making design verification a huge bottleneck for large chip designs. In many companies, verification efforts consume most of the design resources and there are more verification engineers than designers, making verification the real limiter of time to market [1]. Simulation-based verification is the primary means for functional verification. The ever increasing line densities and..