혼성 신호 시스템에서의 확률적 검증과 디버깅 자동화

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 김재하.Increasing system complexity, growing uncertainty in semiconductor technology, and demanding requirements in complex specifications pose significant challenges to both pre-silicon design verification and post-silicon chip validation. Thus, this dissertation investigates efficient pre-silicon/post-silicon validation and debugging methodology, especially for analog and mixed-signal (AMS) systems. Principally, validation is formulated as a Bayesian inference problem and analyzed in a probabilistic manner. For instance, pass/fail property can be checked by Bayesian sampling – the posterior distribution of the unknown failure probability can be measured after many sample validation trials so as to quantify the confidence of pass with a given tolerance and model accuracy. This approach is first taken in the pre-silicon verification to check a systems property. In other words, the efficient Monte Carlo-based methods for ensuring global convergence property are proposed using two techniques: fast sample batch verification using cluster analysis and efficient sampling using Gaussian process regression. In addition, a practical design flow for preventing global convergence failure is presented – the notion of indeterminate state X is extended to AMS systems. For the post-silicon validation, in particular, the probabilistic graphical model is proposed as one effective abstraction of AMS systems. Using the probabilistic graphical model and statistical inference, we can compute the probability of each parameter to satisfy a given specification and use it for bug localization and ranking. The proposed model and method are especially useful at the post-silicon validation phase, since they can check and localize bugs in the system under limited observability and controllability.Contents Abstract Contents List of Tables List of Figures 1 Introduction 2 Probabilistic Validation and Computer-Aided Debugging in AMS Systems 2.1 Validation as Inference 2.2 Bayesian Property Checking by Sampling 2.3 Probabilistic Graphical Models 3 Global Convergence Property Checking withMonte CarloMethods in Pre-Silicon Validation 3.1 Problem Formulation 3.2 Fast Sample Batch Verification using Cluster Analysis 3.2.1 Global convergence failures in state space models 3.2.2 Finding global convergence failures by cluster-split detection 3.2.3 Experimental results 3.3 Efficient Covering and Sampling of Parameter Space 3.3.1 Attempt to cover the parameter space – finding transient regions in circuits state space 3.3.2 Rare-event failure simulation using Gaussian process 3.4 Preventing Global Convergence Failure via Indeterminate State X Elimination 3.4.1 Preventing start-up failure by eliminating all indeterminate states 3.4.2 Procedure of eliminating indeterminate states with the extended X for AMS systems 3.4.3 Reducing reset circuits in the X elimination procedure 3.4.4 Experimental results 4 Bug Localization using Probabilistic GraphicalModels in Post-Silicon Validation 4.1 Problem Formulation 4.2 Modeling of AMS Circuits using Probabilistic Graphical Models 4.2.1 Probabilistic graphical models 4.2.2 Generating probabilistic graphical models for AMS circuits 4.3 Probabilistic Bug Localization using Probabilistic Graphical Models 4.3.1 Posterior estimation using statistical inference 4.3.2 Probabilistic bug localization and ranking 4.3.3 Implementation details 4.4 Experimental Results 4.5 Possible Extensions of Graphical Models – Equivalence Checking 5 Conclusion BibliographyDocto

Functional Verification of Large ASICs

This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASICs designed at Nortel. These devices marked a transition point in methodology as verification took front and centre on the critical path of the ASIC schedule. Both the simulation and emulation strategies are presented. The simulation methodology introduced new techniques such as ASIC sub-system level behavioural modeling, large multi-chip simulations, and random pattern simulations. The emulation strategy was based on a plan that consisted of integrating parts of the real software on the emulated system. This paper describes how these technologies were deployed, analyzes the bugs that were found and highlights the bottlenecks in functional verification as systems become more complex

Functional Verification of Large ASICs

This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASICs designed at Nortel. These devices marked a transition point in methodology as verification took front and centre on the critical path of the ASIC schedule. Both the simulation and emulation strategies are presented. The simulation methodology introduced new techniques such as ASIC sub-system level behavioural modeling, large multi-chip simulations, and random pattern simulations. The emulation strategy was based on a plan that consisted of integrating parts of the real software on the emulated system. This paper describes how these technologies were deployed, analyzes the bugs that were found and highlights the bottlenecks in functional verification as systems become more complex