Использование метода покрытий при верификации моделей IDEF-0

Today’s model driven development of complex software designs requires reliable verification methods. This paper presents metrics of simulation testing and they application in models verification context.Разработка программного обеспечения с использованием моделирования зачастую сталкивается с проблемами ресурсоемкости проверки моделей комплексных систем. Данная статья рассматривает метрические показатели симуляционного тестирования и их применение в контексте непосредственной верификации моделей

Contradictory antecedent debugging in bounded model checking

In the context of formal verification Bounded Model Check-ing (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a temporal property or not. Typically, such a property is for-mulated as an implication. In the antecedent of the property the verification engineer specifies the assumptions about the design environment and joins the respective expressions by logical AND. However, the overall conjunction may have no solution, i.e. the antecedent is contradictory. Since in this case a property trivially holds this situation has to be avoided. Furthermore, the root cause of a contradictory an-tecedent has to be identified which is a manual and very time-consuming process. In this paper we propose a fully automatic approach for presenting all reasons of a contradictory antecedent to the verification engineer, i.e. the approach pinpoints to the sub-expressions in the antecedent that form a contradiction. Hence, our approach reduces the debugging time of a con-tradictory antecedent significantly

Mapping switch-level simulation onto gate-level hardware accelerators

In this paper, we present a framework for performing switch-level simulation on hardware accelerators