2 research outputs found
Formalizing Timing Diagram Requirements in Discrete Duration Calulus
Several temporal logics have been proposed to formalise timing diagram
requirements over hardware and embedded controllers. These include LTL,
discrete time MTL and the recent industry standard PSL. However, succintness
and visual structure of a timing diagram are not adequately captured by their
formulae. Interval temporal logic QDDC is a highly succint and visual notation
for specifying patterns of behaviours.
In this paper, we propose a practically useful notation called SeCeCntnl
which enhances negation free fragment of QDDC with features of nominals and
limited liveness. We show that timing diagrams can be naturally
(compositionally) and succintly formalized in SeCeCntnl as compared with PSL
and MTL. We give a linear time translation from timing diagrams to SeCeCntnl.
As our second main result, we propose a linear time translation of SeCeCntnl
into QDDC. This allows QDDC tools such as DCVALID and DCSynth to be used for
checking consistency of timing diagram requirements as well as for automatic
synthesis of property monitors and controllers. We give examples of a minepump
controller and a bus arbiter to illustrate our tools. Giving a theoretical
analysis, we show that for the proposed SeCeCntnl, the satisfiability and model
checking have elementary complexity as compared to the non-elementary
complexity for the full logic QDDC
DCSYNTH: Guided Reactive Synthesis with Soft Requirements
In reactive controller synthesis, a number of implementations (controllers)
are possible for a given specification because of the incomplete nature of
specification. To choose the most desirable one from the various options, we
need to specify additional properties which can guide the synthesis. In this
paper, We propose a technique for guided controller synthesis from regular
requirements which are specified using an interval temporal logic QDDC. We find
that QDDC is well suited for guided synthesis due to its superiority in dealing
with both qualitative and quantitative specifications. Our framework allows
specification consisting of both hard and soft requirements as QDDC formulas.
We have also developed a method and a tool DCSynth, which computes a
controller that invariantly satisfies the hard requirement and it optimally
meets the soft requirement. The proposed technique is also useful in dealing
with conflicting i.e., unrealizable requirements, by making some of them as
soft requirements. Case studies are carried out to demonstrate the
effectiveness of the soft requirement guided synthesis in obtaining
high-quality controllers. The quality of the synthesized controllers is
compared using metrics measuring both the guaranteed and the expected case
behaviour of the controlled system. Tool DCSynth facilitates such comparison