A novel asynchronous cell library for self-timed system design.

by Eva Yuk-Wah Pang.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.Includes bibliographical references (leaves 88-89).ACKNOWLEDGEMETSABSTRACTLIST OF FIGURESLIST OF TABLESChapter CHAPTER1 --- INTRODUCTIONChapter 1.1 --- Motivation --- p.1-1Chapter 1.1.1 --- Problems with Synchronous Systems --- p.1-1Chapter 1.1.2 --- The Advantages of Self-timed Systems --- p.1-2Chapter 1.1.3 --- Self-Timed Cell Library --- p.1-3Chapter 1.2 --- Overview of the Thesis --- p.1-5Chapter CHAPTER2 --- BACKGROUNDChapter 2.1 --- Introduction --- p.2-1Chapter 2.2 --- Models for Asynchronous System --- p.2-2Chapter 2.2.1 --- Huffman model --- p.2-2Chapter 2.2.2 --- Muller model --- p.2-4Chapter 2.3 --- Self-timed System --- p.2-5Chapter 2.3.1 --- Definitions and Assumptions --- p.2-6Chapter 2.4 --- Design Methodologies --- p.2-8Chapter 2.4.1 --- Differential Logic Structure Design Methodology --- p.2-9Chapter 2.4.1.1 --- Data Path --- p.2-9Chapter 2.4.1.2 --- Control Path --- p.2-10Chapter 2.4.2 --- Micropipeline Design Methodology --- p.2-12Chapter 2.4.2.1 --- Data Path --- p.2-12Chapter 2.4.2.2 --- Control Path --- p.2-13Chapter CHAPTER3 --- SELF-TIMED CELL LIBRARYChapter 3.1 --- Introduction --- p.3-1Chapter 3.2 --- Muller C element --- p.3-1Chapter 3.3 --- Differential Cascode Voltage Switch Logic Circuits --- p.3-6Chapter 3.3.1 --- INVERTER --- p.3-8Chapter 3.3.2 --- "AND, OR, NAND, NOR" --- p.3-8Chapter 3.3.3 --- "XOR, XNOR" --- p.3-10Chapter 3.4 --- Latches --- p.3-11Chapter 3.4.1 --- Precharged Latch --- p.3-12Chapter 3.4.2 --- Capture and Pass Latch --- p.3-12Chapter 3.5 --- Delay Elements --- p.3-13Chapter 3.6 --- Discussion --- p.3-15Chapter CHAPTER4 --- THE CHARACTERISTICS OF SELF-TIMED CELL LIBRARYChapter 4.1 --- Introduction --- p.4-1Chapter 4.2 --- The Simulation Characteristics --- p.4-2Chapter 4.2.1 --- HSPICE program --- p.4-2Chapter 4.2.2 --- Characterization Information and Datasheet terms --- p.4-5Chapter 4.2.3 --- Characterization values --- p.4-6Chapter 4.3 --- The Experimental Analysis --- p.4-6Chapter 4.4 --- Experimental Result and Discussion --- p.4-9Chapter 4.4.1 --- Experimental Result --- p.4-9Chapter 4.4.2 --- Comparison of the characteristics of C-elements --- p.4-12Chapter 4.4.3 --- Comparison of simulation with experimental results --- p.4-13Chapter 4.4.4 --- Properties of DCVSL gate --- p.4-14Chapter 4.4.5 --- The Characteristics of Delay elements --- p.4-15Chapter 4.5 --- CAD Features on Cadence --- p.4-16Chapter CHAPTER5 --- DESIGN EXAMPLE: SELF-TIMED MATRIX MULTIPLIERChapter 5.1 --- Introduction --- p.5-1Chapter 5.2 --- A Matrix Multiplier using DCVSL structure --- p.5-2Chapter 5.2.1 --- Structure --- p.5-2Chapter 5.2.2 --- Handshaking Control Circuit --- p.5-3Chapter 5.2.2.1 --- Handshaking Control Circuit of Pipeline --- p.5-4Chapter 5.2.2.2 --- Handshaking Control Circuit of Feedback Path --- p.5-8Chapter 5.3 --- A Matrix Multiplier using Micropipeline Structure --- p.5-10Chapter 5.3.1 --- Structure --- p.5-10Chapter 5.3.2 --- Control Circuit --- p.5-12Chapter 5.4 --- Experimental Result --- p.5-13Chapter 5.4.1 --- The Matrix Multiplier using DCVSL structure --- p.5-13Chapter 5.4.2 --- The Matrix Multiplier using Micropipeline structure --- p.5-16Chapter 5.5 --- Comparison of DCVSL structure and Micropipeline structure --- p.5-18Chapter CHAPTER6 --- CONCLUSIONChapter 6.1 --- Achievement --- p.6-1Chapter 6.1.1 --- Self-timed Cell Library --- p.6-1Chapter 6.1.2 --- Self-timed System Design simplification --- p.6-2Chapter 6.1.3 --- Area and Speed --- p.6-3Chapter 6.1.4 --- Applications --- p.6-4Chapter 6.2 --- Future work --- p.6-6Chapter 6.2.1 --- Interface with synthesis tools --- p.6-6Chapter 6.2.2 --- Mixed Circuit Design --- p.6-6REFERENCESAPPENDICE