888 research outputs found
A Holistic Approach in Embedded System Development
We present pState, a tool for developing "complex" embedded systems by
integrating validation into the design process. The goal is to reduce
validation time. To this end, qualitative and quantitative properties are
specified in system models expressed as pCharts, an extended version of
hierarchical state machines. These properties are specified in an intuitive way
such that they can be written by engineers who are domain experts, without
needing to be familiar with temporal logic. From the system model, executable
code that preserves the verified properties is generated. The design is
documented on the model and the documentation is passed as comments into the
generated code. On the series of examples we illustrate how models and
properties are specified using pState.Comment: In Proceedings F-IDE 2015, arXiv:1508.0338
Dependability checking with StoCharts: Is train radio reliable enough for trains?
Performance, dependability and quality of service (QoS) are prime aspects of the UML modelling domain. To capture these aspects effectively in the design phase, we have recently proposed STOCHARTS, a conservative extension of UML statechart diagrams. In this paper, we apply the STOCHART formalism to a safety critical design problem. We model a part of the European Train Control System specification, focusing on the risks of wireless communication failures in future high-speed cross-European trains. Stochastic model checking with the model checker PROVER enables us to derive constraints under which the central quality requirements are satisfied by the STOCHART model. The paper illustrates the flexibility and maturity of STOCHARTS to model real problems in safety critical system design
Collaborative Verification-Driven Engineering of Hybrid Systems
Hybrid systems with both discrete and continuous dynamics are an important
model for real-world cyber-physical systems. The key challenge is to ensure
their correct functioning w.r.t. safety requirements. Promising techniques to
ensure safety seem to be model-driven engineering to develop hybrid systems in
a well-defined and traceable manner, and formal verification to prove their
correctness. Their combination forms the vision of verification-driven
engineering. Often, hybrid systems are rather complex in that they require
expertise from many domains (e.g., robotics, control systems, computer science,
software engineering, and mechanical engineering). Moreover, despite the
remarkable progress in automating formal verification of hybrid systems, the
construction of proofs of complex systems often requires nontrivial human
guidance, since hybrid systems verification tools solve undecidable problems.
It is, thus, not uncommon for development and verification teams to consist of
many players with diverse expertise. This paper introduces a
verification-driven engineering toolset that extends our previous work on
hybrid and arithmetic verification with tools for (i) graphical (UML) and
textual modeling of hybrid systems, (ii) exchanging and comparing models and
proofs, and (iii) managing verification tasks. This toolset makes it easier to
tackle large-scale verification tasks
Variations of model checking
The logic ATCTL is a convenient logic to specify properties with actions and real-time. It is intended as a property language for Lightweight UML models [12], which consist mainly of simplified class diagrams and statecharts. ATCTL combines two known extensions of CTL, namely ACTL and TCTL. The reason to extend CTL with both actions and real time is that in LUML stateĀætransition diagrams, we specify states, actions and real time, and our properties refer to all of these elements. The analyst therefore needs a property language that contains constructs for all these elements. ATCTL can be reduced to ACTL as well as to TCTL, and therefore also to CTL. This gives us a choice of tools for model checking; we have used is Kronos [13], a TCTL model checker
Transformation of UML Behavioral Diagrams to Support Software Model Checking
Unified Modeling Language (UML) is currently accepted as the standard for
modeling (object-oriented) software, and its use is increasing in the aerospace
industry. Verification and Validation of complex software developed according
to UML is not trivial due to complexity of the software itself, and the several
different UML models/diagrams that can be used to model behavior and structure
of the software. This paper presents an approach to transform up to three
different UML behavioral diagrams (sequence, behavioral state machines, and
activity) into a single Transition System to support Model Checking of software
developed in accordance with UML. In our approach, properties are formalized
based on use case descriptions. The transformation is done for the NuSMV model
checker, but we see the possibility in using other model checkers, such as
SPIN. The main contribution of our work is the transformation of a non-formal
language (UML) to a formal language (language of the NuSMV model checker)
towards a greater adoption in practice of formal methods in software
development.Comment: In Proceedings FESCA 2014, arXiv:1404.043
A comparative reliability analysis of ETCS train radio communications
StoCharts have been proposed as a UML statechart extension for performance and dependability evaluation, and were applied in the context of train radio reliability assessment to show the principal tractability of realistic cases with this approach. In this paper, we extend on this bare feasibility result in two important directions. First, we sketch the cornerstones of a mechanizable translation of StoCharts to MoDeST. The latter is a process algebra-based formalism supported by the Motor/Mƶbius tool tandem. Second, we exploit this translation for a detailed analysis of the train radio case study
Generic Methodology for Formal Verification of UML Models
This paper discusses a Unified Modelling Language (UML) based formal verification methodology for early error detection in the model-based software development cycle. Our approach proposes a UML-based formal verification process utilising functional and behavioural modelling artifacts of UML. It reinforces these artifacts with formal model transition and property verification. The main contribution is a UML to Labelled Transition System (LTS) Translator application that automatically converts UML Statecharts to formal models. Property specifications are derived from system requirements and corresponding Computational Tree Logic (CTL)/Linear Temporal Logic (LTL) model checking procedure verifies property entailment in LTS. With its ability to verify CTL and LTL specifications, the methodology becomes generic for verifying all types of embedded system behaviours. The steep learning curve associated with formal methods is avoided through the automatic formal model generation and thus reduces the reluctance of using formal methods in software development projects. A case study of an embedded controller used in military applications validates the methodology. It establishes how the methodology finds its use in verifying the correctness and consistency of UML models before implementation
Non-null Infinitesimal Micro-steps: a Metric Temporal Logic Approach
Many systems include components interacting with each other that evolve with
possibly very different speeds. To deal with this situation many formal models
adopt the abstraction of "zero-time transitions", which do not consume time.
These however have several drawbacks in terms of naturalness and logic
consistency, as a system is modeled to be in different states at the same time.
We propose a novel approach that exploits concepts from non-standard analysis
to introduce a notion of micro- and macro-steps in an extension of the TRIO
metric temporal logic, called X-TRIO. We use X-TRIO to provide a formal
semantics and an automated verification technique to Stateflow-like notations
used in the design of flexible manufacturing systems.Comment: 20 pages, 2 figures, submitted to the conference "FORMATS: Formal
Modelling and Analysis of Timed Systems" 201
- ā¦