Formal Verification of Timed VHDL Programs

International audienceThe verification of timed digital circuits is an important issue. These circuits are composed by logical gates, each of them being associated with propagation delays. The analysis of such circuits is necessary to identify critical path and adjust the clock period of the circuit or to determine the stability period of input/ouput signals. These circuits are represented by a functional model described in VHDL and a timing model associating propagation delays to each functional block. This model is translated into timed automata formalism upon which classical simulation or model checking verification can be performed. This method rises two problems: 1) Propagation delays associated to a gate depend on the transistor assembly and the manufacturer's technology. How do we associate propagation delays to a logical gate ? 2) How to automatically translate a VHDL functional description, combined with propagation delays, into timed automata ? This paper addresses these two problems. It presents a method automating the verification of VHDL descriptions, augmented with interval bounded propagation delays, obtained by electrical simulation of the transistor model of the gates