CORE
🇺🇦Â
 make metadata, not war
Services
Services overview
Explore all CORE services
Access to raw data
API
Dataset
FastSync
Content discovery
Recommender
Discovery
OAI identifiers
OAI Resolver
Managing content
Dashboard
Bespoke contracts
Consultancy services
Support us
Support us
Membership
Sponsorship
Community governance
Advisory Board
Board of supporters
Research network
About
About us
Our mission
Team
Blog
FAQs
Contact us
Filters
1 research outputs found
Formal Modeling and Verification of Controllers for a Family of DRAM Caches
Author
Debiprasanna Sahoo
Madhu Mutyam
+4Â more
Manoranjan Satpathy
Partha Roop
S. Ramesh
Swaraj Sha
Publication venue
'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date
Field of study
No full text
Crossref
No full text
