Test Scheduling of SoC by using Dynamic Voltage Frequency Scaling (DVFS) Technique

High temperature gradients in System on Chip (SoC) lowered the performances, reliability and leakage power. In addition, temperature during testing gain more compared to normal operation. Therefore, the investigation of the impact dynamic voltage frequency scaling (DVFS) on the thermal aware test scheduling performance will be the main contribution of this work. The test scheduling algorithm which embeds frequency scaling effect with dynamic voltage supply is tested on ITC’02 benchmark. The formulation of ILP is to minimize the group of the test session in SoC and continued with DVFS formulation. Compared to the conventional thermal-aware scheduling approach based purely on a frequency scaling, this technique provides shorter overall test times and greatly improved flexibility to satisfy strict thermal constraints. The proposed DVFS with thermal aware task scheduling allows to minimize test time more than 46%

Finding Best Voltage and Frequency to Shorten Power-Constrained Test Time

Abstract—In a digital test, supply voltage (VDD), clock frequency (ftest), peak power (PMAX) and test time (TT) are related parameters. For a given limit PMAX = PMAXfunc, normally set by functional specification, we find the optimum VDD = VDDopt and ftest = fopt to minimize TT. A solution is derived analytically from the technology-dependent characterization of semiconductor devices. It is shown that at VDDopt the peak power any test cycle consumes just equals PMAXfunc and ftest is fastest that the critical path at VDDopt will allow. The paper demonstrates how test parameters can be obtained numerically from MATLAB, or experimentally by bench test equipment like National Instruments ’ ELVIS. This optimization can cut the test time of ISCAS’89 benchmarks in 180nm CMOS into half. Keywords-Reduced voltage test, Test time reduction, Scan test. I