A novel fault-tolerant control strategy for near space hypersonic vehicles via least squares support vector machine and backstepping method

Near Space Hypersonic Vehicle (NSHV) could play significant roles in both military and civilian applications. It may cause huge losses of both personnel and property when a fatal fault occurs. It is therefore paramount to conduct fault-tolerant research for NSHV and avoid some catastrophic events. Toward this end, this paper presents a novel fault-tolerant control strategy by using the LSSVM (Least Squares Support Vector Machine)-based inverse system and Backstepping method. The control system takes advantage of the superiority of the LSSVM in solving the problems with small samples, high dimensions and local minima. The inverse system is built with an improved LSSVM. The adaptive controller is designed via the Backstepping which has the unique capability in dealing with nonlinear control systems. Finally, the experiment results demonstrate that the proposed method performs well

Fault-tolerant fpga for mission-critical applications.

One of the devices that play a great role in electronic circuits design, specifically safety-critical design applications, is Field programmable Gate Arrays (FPGAs). This is because of its high performance, re-configurability and low development cost. FPGAs are used in many applications such as data processing, networks, automotive, space and industrial applications. Negative impacts on the reliability of such applications result from moving to smaller feature sizes in the latest FPGA architectures. This increases the need for fault-tolerant techniques to improve reliability and extend system lifetime of FPGA-based applications. In this thesis, two fault-tolerant techniques for FPGA-based applications are proposed with a built-in fault detection region. A low cost fault detection scheme is proposed for detecting faults using the fault detection region used in both schemes. The fault detection scheme primarily detects open faults in the programmable interconnect resources in the FPGAs. In addition, Stuck-At faults and Single Event Upsets (SEUs) fault can be detected. For fault recovery, each scheme has its own fault recovery approach. The first approach uses a spare module and a 2-to-1 multiplexer to recover from any fault detected. On the other hand, the second approach recovers from any fault detected using the property of Partial Reconfiguration (PR) in the FPGAs. It relies on identifying a Partially Reconfigurable block (P_b) in the FPGA that is used in the recovery process after the first faulty module is identified in the system. This technique uses only one location to recover from faults in any of the FPGA’s modules and the FPGA interconnects. Simulation results show that both techniques can detect and recover from open faults. In addition, Stuck-At faults and Single Event Upsets (SEUs) fault can also be detected. Finally, both techniques require low area overhead