Subsurface optical microscopy of semiconductor integrated circuits

Thesis (Ph.D.)--Boston UniversityThe semiconductor industry continues to scale integrated circuits (ICs) in accordance with Moore's Law, and is currently developing the processing infrastructure at the 14nm technology node and smaller. In the wake of such rapid progress, a number of challenges have arisen for the optical failure analysis methods to meet the requirements of the advancing process technology. Most notably, complex circuits with shrinking critical dimensions will demand higher resolution signal localization currently beyond the capability of the existing optical techniques. This dissertation aims to develop novel optical systems to address the challenges of non-destructive circuit diagnostics at the 14nm technology node and beyond. Backside imaging through the silicon substrate has become an industry standard due to the dense multi-level metal wiring and the packaging requirements. The solid immersion lens is a plano-convex lens placed on the planar silicon substrate to enhance the subsurface focusing and collection of light in back-side imaging of ICs. The silicon and gallium-arsenide aplanatic solid immersion lenses (aSILs) were investigated in detail for the subsurface laser-scanning, voltage modulation, photon emission and dark-field IC imaging applications. Wave-front sensing and shaping techniques were developed to evaluate and mitigate optical aberrations originating from practical issues. Furthermore, the method of pupil function tailoring was explored for sub-diffraction spatial resolution. Super-resolving annular phase and amplitude pupil masks were developed and experimentally implemented. A record-breaking light confinement of 0.02 λ2 0(λ 0 refers to the free-space wavelength) was demonstrated using the vortex beams. The beam invasiveness is a critical issue in the optical circuit probing as the localized heat due to the absorption of the focused beams may unwittingly interfere with the circuit operation in the course of a measurement. A dual-phase interferometry assisted circuit probing was developed to enhance the signal extraction sensitivity by as much as an order of magnitude. Thus, the power requirement of the probe beam is significantly reduced to avert the consequences of the beam invasiveness. The optical systems and methods developed in this dissertation were successfully demonstrated using a number of modern ICs including devices of 14nm, 22nm, 28nm and 32nm technology nodes

Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge.

Today, design verification is by far the most resource and time-consuming activity of any new digital integrated circuit development. Within this area, the vast majority of the verification effort in industry relies on simulation platforms, which are implemented either in hardware or software. A "simulator" includes a model of each component of a design and has the capability of simulating its behavior under any input scenario provided by an engineer. Thus, simulators are deployed to evaluate the behavior of a design under as many input scenarios as possible and to identify and debug all incorrect functionality. Two features are critical in simulators for the validation effort to be effective: performance and checking/debugging capabilities. A wide range of simulator platforms are available today: on one end of the spectrum there are software-based simulators, providing a very rich software infrastructure for checking and debugging the design's functionality, but executing only at 1-10 simulation cycles per second (while actual chips operate at GHz speeds). At the other end of the spectrum, there are hardware-based platforms, such as accelerators, emulators and even prototype silicon chips, providing higher performances by 4 to 9 orders of magnitude, at the cost of very limited or non-existent checking/debugging capabilities. As a result, today, simulation-based validation is crippled: one can either have satisfactory performance on hardware-accelerated platforms or critical infrastructures for checking/debugging on software simulators, but not both. This dissertation brings together these two ends of the spectrum by presenting solutions that offer high-performance simulation with effective checking and debugging capabilities. Specifically, it addresses the performance challenge of software simulators by leveraging inexpensive off-the-shelf graphics processors as massively parallel execution substrates, and then exposing the parallelism inherent in the design model to that architecture. For hardware-based platforms, the dissertation provides solutions that offer enhanced checking and debugging capabilities by abstracting the relevant data to be logged during simulation so to minimize the cost of collection, transfer and processing. Altogether, the contribution of this dissertation has the potential to solve the challenge of digital design verification by enabling effective high-performance simulation-based validation.PHDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/99781/1/dchatt_1.pd