Reversible circuits with testability using quantum controlled NOT and swap gates

A new method of designing reversible circuits with inbuilt testability is presented by exploiting the properties of quantum controlled NOT and Swap gates. The design process is based on the methodology of placement of gates in such a manner that it produces parity preserving circuits. The testability of these circuits can be achieved by comparing the input and output parity under single bit fault detection. Experiments are conducted on a set of benchmark circuits which show an average reduction up to 51% in operating costs, when compared to existing work

Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.Comment: 9 pages, 7 figures, 5 table

A review on reversible logic gates

In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.   Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic

Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

Energy dissipation is a prominent factor for the very large scale integrated circuit (VLSI). The reversible logic-based circuit was capable to compute the logic without energy dissipation. Accordingly, reversible circuits are an emerging domain of research based on the low value of energy dissipation. At nano-level design, the critical factor in the logic computing paradigm is the fault. The proposed methodology of fault coverage is powerful for testability. In this article, we target three factors such as fault tolerance, fault coverage and fault detection in the reversible KMD Gates. Our analysis provides good evidence that the minimum test vector covers the 100 % fault coverage and 50 % fault tolerance in KMD Gate. Further, we show a comparison between the quantum equivalent and controlled V and V+ gate in all the types of KMD Gates. The proposed methodology mentions that after controlled V and V+ gate based ALU, divider and Vedic multiplier have a significant reduction in quantum cost. The comparative results of designs such as Vedic multiplier, division unit and ALU are obtained and they are analyzed showing significant improvement in quantum cost

Design & Performance Analysis of 8-Bit Low Power Parity Preserving Carry-Look Ahead Adder

In the field of quantum computation, the reversible logic and nanotechnology has gathered a lot of attention of researcher’s in the recent years due to its low power dissipation quality. Quantum computing has been a guiding light for nanotechnology, optical information computing, low power CMOS design, DNA computing and Low power VLSI design. Parity preserving is one of the oldest method for error correction and detection in digital system design. In this paper we proposed two parity preserving reversible 8-bit carry look ahead adder circuits. First circuit is designed usingFredkin Gates and Double Feynman (F2G) Gates, while second circuit is designed using Double Feynman (F2G) Gates and Modified Fredkin Gates. By comparing both circuits, we demonstrate that our second proposed design of reversible parity preserving circuit is optimized in terms of quantum cost and power consumption

Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit

With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design