680 research outputs found
Fast-SSC-Flip Decoding of Polar Codes
Polar codes are widely considered as one of the most exciting recent
discoveries in channel coding. For short to moderate block lengths, their
error-correction performance under list decoding can outperform that of other
modern error-correcting codes. However, high-speed list-based decoders with
moderate complexity are challenging to implement. Successive-cancellation
(SC)-flip decoding was shown to be capable of a competitive error-correction
performance compared to that of list decoding with a small list size, at a
fraction of the complexity, but suffers from a variable execution time and a
higher worst-case latency. In this work, we show how to modify the
state-of-the-art high-speed SC decoding algorithm to incorporate the SC-flip
ideas. The algorithmic improvements are presented as well as average
execution-time results tailored to a hardware implementation. The results show
that the proposed fast-SSC-flip algorithm has a decoding speed close to an
order of magnitude better than the previous works while retaining a comparable
error-correction performance.Comment: 5 pages, 3 figures, appeared at IEEE Wireless Commun. and Netw. Conf.
(WCNC) 201
Rate-Flexible Fast Polar Decoders
Polar codes have gained extensive attention during the past few years and
recently they have been selected for the next generation of wireless
communications standards (5G). Successive-cancellation-based (SC-based)
decoders, such as SC list (SCL) and SC flip (SCF), provide a reasonable error
performance for polar codes at the cost of low decoding speed. Fast SC-based
decoders, such as Fast-SSC, Fast-SSCL, and Fast-SSCF, identify the special
constituent codes in a polar code graph off-line, produce a list of operations,
store the list in memory, and feed the list to the decoder to decode the
constituent codes in order efficiently, thus increasing the decoding speed.
However, the list of operations is dependent on the code rate and as the rate
changes, a new list is produced, making fast SC-based decoders not
rate-flexible. In this paper, we propose a completely rate-flexible fast
SC-based decoder by creating the list of operations directly in hardware, with
low implementation complexity. We further propose a hardware architecture
implementing the proposed method and show that the area occupation of the
rate-flexible fast SC-based decoder in this paper is only of the total
area of the memory-based base-line decoder when 5G code rates are supported
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