Fast sequential circuit test generation using high-level and gate-level techniques

A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements in a high-level VHDL description, or to maximize coverage of paths. The sequences are then enhanced at the gate level to maximize coverage of single stuck-at faults. High fault coverages have been achieved very quickly on several benchmark circuits using this approach. 1 Introduction Most recent work in the area of sequential circuit test generation has focused on the gate level and has been targeted at single stuck-at faults. Both deterministic fault-oriented and simulation-based approaches have been used e#ectively, although execution times are often long. The key factor limiting the e#ciency of these approaches has been the lack of knowledge about circuit behavior. Architectural-level test generation has been proposed as a means ..