FAILURE-SENSITIVE ANALYSIS OF PARALLEL ALGORITHMS WITH CONTROLLED MEMORY ACCESS CONCURRENCY£

Abstract: The abstract problem of usingÈfailure-prone processors to cooperatively update all locations of anÆ-element shared array is called Write-All. Solutions to Write-All can be used iteratively to construct efficient simulations of PRAM algorithms on failure-prone PRAMs. Such use of Write-All in simulations is abstracted in terms of the iterative Write-All problem. The efficiency of the algorithmic solutions for Write-All and iterative Write-All is measured in terms of work complexity where all processing steps taken by the processors are counted. This paper considers solutions for the Write-All and iterative Write-All problems in the fail-stop synchronous CRCW PRAM model where memory access concurrency needs to be controlled. Algorithm KMS [KMS95] efficiently solves the Write-All problem in this model, while controlling read and write memory access concurrency. However it was not shown how the number of processor failures�affects the work efficiency of the algorithm. The results herein give a new analysis of algorithm KMS that obtain failure-sensitive work bounds, while maintaining the known memory access concurrency bounds. Specifically, the new result expresses the work bound as a function ofÆ,Èand�. Another contribution in this paper is the new failure-sensitive analysis for iterative Write-All with controlled memory access concurrency. This result yields tighter bounds on work (vs. [KMS95]) for simulations of PRAM algorithms on fail-stop PRAMs