Abstract FPGA Based Fault Emulation of Synchronous Sequential Circuits

This paper describes a feasibiliiy siudy of accelerating fault simulation by emulation on FPGA. Fault simulation b an important subtask in test pattem generation and it isfiequently used throughout the test generation process. In order to further speed up simulalion, we propose to make use of reconjgurable hardware by emulating cir-cuit together with fault insertion siructures on FPGA. Experiments showed that it is beneficial to use emulation for circuitdmethoak that require large numbers of test vectors, e.g., sequential circuits and/or genetic algo-rithms. 1