FPGA implementation of a synchronous and self-timed neuroprocessor

This article presents the implementation of a neuroprocessor based on a self-organizing map (SOM) architecture. The processor presents a hybrid structure both synchronous and self-timed. Where the neuronal network blocks (SOM) are synchronized with a protocol of 4 phases, for the control of data flow. The neuroprocessor was designed for the analysis and classification of tension deformation patterns of the knee ligaments. The circuit is programmable and recognizes different sequences of movement patterns for a knee joint with damage to the anterior cruciate ligament (ACL). This design is part of an electronic system for the rehabilitation of injuries to the ACL and the dynamic study of the knee. The circuit is implemented in an FPGA Virtex II. 1