Frequency diversity wideband digital receiver and signal processor for solid-state dual-polarimetric weather radars

2012 Summer.Includes bibliographical references.The recent spate in the use of solid-state transmitters for weather radar systems has unexceptionably revolutionized the research in meteorology. The solid-state transmitters allow transmission of low peak powers without losing the radar range resolution by allowing the use of pulse compression waveforms. In this research, a novel frequency-diversity wideband waveform is proposed and realized to extenuate the low sensitivity of solid-state radars and mitigate the blind range problem tied with the longer pulse compression waveforms. The latest developments in the computing landscape have permitted the design of wideband digital receivers which can process this novel waveform on Field Programmable Gate Array (FPGA) chips. In terms of signal processing, wideband systems are generally characterized by the fact that the bandwidth of the signal of interest is comparable to the sampled bandwidth; that is, a band of frequencies must be selected and filtered out from a comparable spectral window in which the signal might occur. The development of such a wideband digital receiver opens a window for exciting research opportunities for improved estimation of precipitation measurements for higher frequency systems such as X, Ku and Ka bands, satellite-borne radars and other solid-state ground-based radars. This research describes various unique challenges associated with the design of a multi-channel wideband receiver. The receiver consists of twelve channels which simultaneously downconvert and filter the digitized intermediate-frequency (IF) signal for radar data processing. The product processing for the multi-channel digital receiver mandates a software and network architecture which provides for generating and archiving a single meteorological product profile culled from multi-pulse profiles at an increased data date. The multi-channel digital receiver also continuously samples the transmit pulse for calibration of radar receiver gain and transmit power. The multi-channel digital receiver has been successfully deployed as a key component in the recently developed National Aeronautical and Space Administration (NASA) Global Precipitation Measurement (GPM) Dual-Frequency Dual-Polarization Doppler Radar (D3R). The D3R is the principal ground validation instrument for the precipitation measurements of the Dual Precipitation Radar (DPR) onboard the GPM Core Observatory satellite scheduled for launch in 2014. The D3R system employs two broadly separated frequencies at Ku- and Ka-bands that together make measurements for precipitation types which need higher sensitivity such as light rain, drizzle and snow. This research describes unique design space to configure the digital receiver for D3R at several processing levels. At length, this research presents analysis and results obtained by employing the multi-carrier waveforms for D3R during the 2012 GPM Cold-Season Precipitation Experiment (GCPEx) campaign in Canada

DESIGN AND IMPLEMENTATION OF LIFTING BASED DAUBECHIES WAVELET TRANSFORMS USING ALGEBRAIC INTEGERS

Over the past few decades, the demand for digital information has increased drastically. This enormous demand poses serious difficulties on the storage and transmission bandwidth of the current technologies. One possible solution to overcome this approach is to compress the amount of information by discarding all the redundancies. In multimedia technology, various lossy compression techniques are used to compress the raw image data to facilitate storage and to fit the transmission bandwidth. In this thesis, we propose a new approach using algebraic integers to reduce the complexity of the Daubechies-4 (D4) and Daubechies-6 (D6) Lifting based Discrete Wavelet Transforms. The resulting architecture is completely integer based, which is free from the round-off error that is caused in floating point calculations. The filter coefficients of the two transforms of Daubechies family are individually converted to integers by multiplying it with value of 2x, where, x is a random value selected at a point where the quantity of losses is negligible. The wavelet coefficients are then quantized using the proposed iterative individual-subband coding algorithm. The proposed coding algorithm is adopted from the well-known Embedded Zerotree Wavelet (EZW) coding. The results obtained from simulation shows that the proposed coding algorithm proves to be much faster than its predecessor, and at the same time, produces good Peak Signal to Noise Ratio (PSNR) at very low bit rates. Finally, the two proposed transform architectures are implemented on Virtex-E Field Programmable Gate Array (FPGA) to test the hardware cost (in terms of multipliers, adders and registers) and throughput rate. From the synthesis results, we see that the proposed algorithm has low hardware cost and a high throughput rate

Discrete Wavelet Transforms

The discrete wavelet transform (DWT) algorithms have a firm position in processing of signals in several areas of research and industry. As DWT provides both octave-scale frequency and spatial timing of the analyzed signal, it is constantly used to solve and treat more and more advanced problems. The present book: Discrete Wavelet Transforms: Algorithms and Applications reviews the recent progress in discrete wavelet transform algorithms and applications. The book covers a wide range of methods (e.g. lifting, shift invariance, multi-scale analysis) for constructing DWTs. The book chapters are organized into four major parts. Part I describes the progress in hardware implementations of the DWT algorithms. Applications include multitone modulation for ADSL and equalization techniques, a scalable architecture for FPGA-implementation, lifting based algorithm for VLSI implementation, comparison between DWT and FFT based OFDM and modified SPIHT codec. Part II addresses image processing algorithms such as multiresolution approach for edge detection, low bit rate image compression, low complexity implementation of CQF wavelets and compression of multi-component images. Part III focuses watermaking DWT algorithms. Finally, Part IV describes shift invariant DWTs, DC lossless property, DWT based analysis and estimation of colored noise and an application of the wavelet Galerkin method. The chapters of the present book consist of both tutorial and highly advanced material. Therefore, the book is intended to be a reference text for graduate students and researchers to obtain state-of-the-art knowledge on specific applications

WAVELET-DCT BASED IMAGE CODER FOR VIDEO CODING APPLICATIONS

This project is about the implementation ofWavelet-DCT intra-frame coder for video coding applications. Wavelet-DCT is a novel algorithm that uses Forward Discrete Wavelet Transform (DWT) to compute DCT. It is proved that the algorithm has better compression performance for difference images compared to conventional DCT. This is possible since the algorithm allows discarding insignificant DWT coefficients or more popularly known thresholding the DWT coefficients while computing the DCT. In video coder applications, wavelet-DCT is capable to achieve greater compression. This project is a feasibility study on the performance ofWavelet-DCT in video coder applications. ASIMULINK model for conventional intra-frame coder is developed and tested, with very significant data bit reduction achieved. Then, the conventional DCT block has been replaced with a Wavelet-DCT block. In the study, on one hand, experiment is conducted on difference image for conventional intra-frame coder; on the other, the same difference image with Wavelet-DCT based intra-frame coder. The thresholding algorithm is used to remove some ofthe insignificant DWT coefficients from the difference image. The main objective is to achieve a better compression capability for difference image within video coding applications. The project's experimental results supports our claim that implementation ofWavelet-DCT in intraframe coder within a video coding application could improve the system's performance with a greater compression ratio at the same Mean Squared Error

Digital FPGA Circuits Design for Real-Time Video Processing with Reference to Two Application Scenarios

In the present days of digital revolution, image and/or video processing has become a ubiquitous task: from mobile devices to special environments, the need for a real-time approach is everyday more and more evident. Whatever the reason, either for user experience in recreational or internet-based applications or for safety related timeliness in hard-real-time scenarios, the exploration of technologies and techniques which allow for this requirement to be satisfied is a crucial point. General purpose CPU or GPU software implementations of these applications are quite simple and widespread, but commonly do not allow high performance because of the high layering that separates high level languages and libraries, which enforce complicated procedures and algorithms, from the base architecture of the CPUs that offers only limited and basic (although rapidly executed) arithmetic operations. The most practised approach nowadays is based on the use of Very-Large-Scale Integrated (VLSI) digital electronic circuits. Field Programmable Gate Arrays (FPGAs) are integrated digital circuits designed to be configured after manufacturing, "on the field". They typically provide lower performance levels when compared to Application Specific Integrated Circuits (ASICs), but at a lower cost, especially when dealing with limited production volumes. Of course, on-the-field programmability itself (and re-programmability, in the vast majority of cases) is also a characteristic feature that makes FPGA more suitable for applications with changing specifications where an update of capabilities may be a desirable benefit. Moreover, the time needed to fulfill the design cycle for FPGA-based circuits (including of course testing and debug speed) is much reduced when compared to the design flow and time-to-market of ASICs. In this thesis work, we will see (Chapter 1) some common problems and strategies involved with the use of FPGAs and FPGA-based systems for Real Time Image Processing and Real Time Video Processing (in the following alsoindicated interchangeably with the acronym RTVP); we will then focus, in particular, on two applications. Firstly, Chapter 2 will cover the implementation of a novel algorithm for Visual Search, known as CDVS, which has been recently standardised as part of the MPEG-7 standard. Visual search is an emerging field in mobile applications which is rapidly becoming ubiquitous. However, typically, algorithms for this kind of applications are connected with a high leverage on computational power and complex elaborations: as a consequence, implementation efficiency is a crucial point, and this generally results in the need for custom designed hardware. Chapter 3 will cover the implementation of an algorithm for the compression of hyperspectral images which is bit-true compatible with the CCSDS-123.0 standard algorithm. Hyperspectral images are three dimensional matrices in which each 2D plane represents the image, as captured by the sensor, in a given spectral band: their size may range from several millions of pixels up to billions of pixels. Typical scenarios of use of hyperspectral images include airborne and satellite-borne remote sensing. As a consequence, major concerns are the limitedness of both processing power and communication links bandwidth: thus, a proper compression algorithm, as well as the efficiency of its implementation, is crucial. In both cases we will first of all examine the scope of the work with reference to current state-of-the-art. We will then see the proposed implementations in their main characteristics and, to conclude, we will consider the primary experimental results

A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 9292m for the implemented digital-backend

A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 92×92µm for the implemented digital-backend

Development of novel ultrasound techniques for imaging and elastography. From simulation to real-time implementation

Ultrasound techniques offer many advantages, in terms of ease of realization and patients’ safety. The availability of suitable hardware and software tools is condicio sine qua non for new methods testing. This PhD project addresses medical ultrasound signal processing and seeks to achieve two scientific goals: the first is to contribute to the development of an ultrasound research platform, while the second is introducing and validating, through this platform, non-standard methods. During the thesis, the capabilities of the system were improved by creating advanced software tools, such as acoustic field simulators, and by developing echo-signals elaboration programs. In particular, a novel technique for quasi-static elastography was developed, in-vitro tested and implemented in real-time

Architectures for Adaptive Low-Power Embedded Multimedia Systems

This Ph.D. thesis describes novel hardware/software architectures for adaptive low-power embedded multimedia systems. Novel techniques for run-time adaptive energy management are proposed, such that both HW & SW adapt together to react to the unpredictable scenarios. A complete power-aware H.264 video encoder was developed. Comparison with state-of-the-art demonstrates significant energy savings while meeting the performance constraint and keeping the video quality degradation unnoticeable

A wavelet-based CMAC for enhanced multidimensional learning

The CMAC (Cerebellar Model Articulation Controller) neural network has been successfully used in control systems and other applications for many years. The network structure is modular and associative, allowing for rapid learning convergence with an ease of implementation in either hardware or software. The rate of convergence of the network is determined largely by the choice of the receptive field shape and the generalization parameter. This research contains a rigorous analysis of the rate of convergence with the standard CMAC, as well as the rate of convergence of networks using other receptive field shape. The effects of decimation from state-space to weight space are examined in detail. This analysis shows CMAC to be an adaptive lowpass filter, where the filter dynamics are governed by the generalization parameter. A more general CMAC is derived using wavelet-based receptive fields and a controllable decimation scheme, that is capable of convergence at any frequency within the Nyquist limits. The flexible decimation structure facilitates the optimization of computation for complex multidimensional problems. The stability of the wavelet-based CMAC is also examined