FPGA generators of combinatorial configurations in a linear array model

In this paper we describe hardware implementations of generators of combinatorial objects. For implementation several systolic algorithms were selected that generate combinatorial configurations in a linear array model. The algorithms generate such objects as combinations, combinations with repetitions, t–ary trees, partitions, and variations with repetitions. The generators were implemented in VHLD with Xilinx Foundation ISE software and tested on Digilent development boards with Xilinx FPGAs. Implementation data obtained for various input parameters and FPGA devices are given

2008 International Symposium on Parallel and Distributed Computing FPGA generators of combinatorial configurations in a linear array model

In this paper we describe hardware implementations of generators of combinatorial objects. For implementation several systolic algorithms were selected that generate combinatorial configurations in a linear array model. The algorithms generate such objects as combinations, combinations with repetitions, t–ary trees, partitions, and variations with repetitions. The generators were implemented in VHLD with Xilinx Foundation ISE software and tested on Digilent development boards with Xilinx FPGAs. Implementation data obtained for various input parameters and FPGA devices are given