EDAC software implementation to protect small satellites memory

Radiation is a well-known problem for satellites in space. It can produce different negative effects on electronic components which can provoke errors and failures. Therefore, mitigating these effects is especially important for the success of space missions. One of the techniques to increase the reliability of memory chips and reduce transient errors and permanent faults is Error Detection and Correction (EDAC). EDAC codes are characterised by the use of redundancy to detect and correct errors. This final project consists in the implementation of a software EDAC algorithm to protect the main memory of a microcontroller. The implementation requirements and the issues of software EDAC are described and the test results are commented

Innovative actuator fault identification based on back electromotive force reconstruction

The ever increasing adoption of electrical power as secondary form of on-board power is leading to an increase in the usage of electromechanical actuators (EMAs). Thus, in order to maintain an acceptable level of safety and reliability, innovative prognostics and diagnostics methodologies are needed to prevent performance degradation and/or faults propagation. Furthermore, the use of effective prognostics methodologies carries several benefits, including improved maintenance schedule capability and relative cost decrease, better knowledge of systems health status and performance estimation. In this work, a novel, real-time approach to EMAs prognostics is proposed. The reconstructed back electromotive force (back-EMF), determined using a virtual sensor approach, is sampled and then used to train an artificial neural network (ANN) in order to evaluate the current system status and to detect possible coils partial shorts and rotor imbalances

Advanced information processing system: Fault injection study and results

The objective of the AIPS program is to achieve a validated fault tolerant distributed computer system. The goals of the AIPS fault injection study were: (1) to present the fault injection study components addressing the AIPS validation objective; (2) to obtain feedback for fault removal from the design implementation; (3) to obtain statistical data regarding fault detection, isolation, and reconfiguration responses; and (4) to obtain data regarding the effects of faults on system performance. The parameters are described that must be varied to create a comprehensive set of fault injection tests, the subset of test cases selected, the test case measurements, and the test case execution. Both pin level hardware faults using a hardware fault injector and software injected memory mutations were used to test the system. An overview is provided of the hardware fault injector and the associated software used to carry out the experiments. Detailed specifications are given of fault and test results for the I/O Network and the AIPS Fault Tolerant Processor, respectively. The results are summarized and conclusions are given

Sustainable Fault-handling Of Reconfigurable Logic Using Throughput-driven Assessment

A sustainable Evolvable Hardware (EH) system is developed for SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) using outlier detection and group testing-based assessment principles. The fault diagnosis methods presented herein leverage throughput-driven, relative fitness assessment to maintain resource viability autonomously. Group testing-based techniques are developed for adaptive input-driven fault isolation in FPGAs, without the need for exhaustive testing or coding-based evaluation. The techniques maintain the device operational, and when possible generate validated outputs throughout the repair process. Adaptive fault isolation methods based on discrepancy-enabled pair-wise comparisons are developed. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, a method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. The results from the analytical FPGA model are demonstrated via a self-healing, self-organizing evolvable hardware system. Reconfigurability of the SRAM-based FPGA is leveraged to identify logic resource faults which are successively excluded by group testing using alternate device configurations. This simplifies the system architect\u27s role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance versus availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an Observer-Controller model. Results are demonstrated using a Data Encryption Standard (DES) core that occupies approximately 305 FPGA slices on a Xilinx Virtex-II Pro FPGA. With a single simulated stuck-at-fault, the system identifies a completely validated replacement configuration within three to five positive tests. The approach demonstrates a readily-implemented yet robust organic hardware application framework featuring a high degree of autonomous self-control

Observation of Electric-Field-Induced Structural Dislocations in a Ferroelectric Oxide

Dislocations are 1D topological defects with emergent electronic properties. Their low dimensionality and unique properties make them excellent candidates for innovative device concepts, ranging from dislocation-based neuromorphic memory to light emission from diodes. To date, dislocations are created in materials during synthesis via strain fields or flash sintering or retrospectively via deformation, for example, (nano)-indentation, limiting the technological possibilities. In this work, we demonstrate the creation of dislocations in the ferroelectric semiconductor Er(Mn,Ti)O3 with nanoscale spatial precision using electric fields. By combining high-resolution imaging techniques and density functional theory calculations, direct images of the dislocations are collected, and their impact on the local electric transport behavior is studied. Our approach enables local property control via dislocations without the need for external macroscopic strain fields, expanding the application opportunities into the realm of electric-field-driven phenomena.publishedVersio

AirTight: A Resilient Wireless Communication Protocol for Mixed-Criticality Systems

This paper describes the motivation, design, analysis and implementation of a new protocol for critical wireless communication called AirTight. Wireless communication has become a crucial part of the infrastructure of many cyber-physical applications. Many of these applications are real-time and also mixed-criticality, in that they have components/subsystems with different consequences of failure. Wireless communication is inevitably subject to levels of external interference. In this paper we represent this interference using a criticality-aware fault model; for each level of interference in the fault model we guarantee the timing behaviour of the protocol (i.e.~we guarantee that packet deadlines are satisfied for certainly levels of criticality). Although a new protocol, AirTight is built upon existing standards such as IEEE 802.15.4. A prototype implementation and protocol-accurate simulator, which are also built upon existing technologies, demonstrate the effectiveness and functionality of the protocol