Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design

Neiriory desigii is faciiig the upcorriiiig clialleiiges due to a coriibiiiatioii of ' techriology scaliiig aiid higher levels of iiiteteiri coriiplexity. Iii particular, rneriioi-y circuits bccoiric vuliicrablc to traiisiciit (soft) errors caused by particle strikes aiid process spread. In this paper; we propose a iicw error-tolcraiicc tccliiiiquc rcfcrrcd to as the sojt reduriduricy for on-chip rneiriory design. Program ruritiirie variatioiis iii rrierriory spatial locality cause wasted rrieriiory spaces occupied by tlic irrclcvaiit data. Tlic proposed softreduiidaiicy allocated riieriioi-y exploits these wasted riieriiory spaces to acliicvc cfficiciit iriciriory access aid effective error protection iri a coherent riiaiiiier. Sirriulatiori results oii the SPEC CPU2000 bciicliriiarks dcirioiistratc 73.7 % a\-erage error protectioii coverage ratio oii the 23 beiicliriiarl<s: with average of 52%) aid 48.3%) reductioii iii irierriory miss rate aiid baiidwidth rcquirciriciit. respectively. as corriparcd to the existing techiiiques