Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture

Abstract: In our previously published research we discovered some very difficult to predict branches, called unbiased branches. Since the overall performance of modern processors is seriously affected by misprediction recovery, especially these difficult branches represent a source of important performance penalties. Our statistics show that about 28 % of branches are dependent on critical Load instructions. Moreover, 5.61 % of branches are unbiased and depend on critical Loads, too. In the same way, about 21 % of branches depend on MUL/DIV instructions whereas 3.76 % are unbiased and depend on MUL/DIV instructions. These dependences involve high-penalty mispredictions becoming serious performance obstacles and causing significant performance degradation in executing instructions from wrong paths. Therefore, the negative impact of (unbiased) branches over global performance should be seriously attenuated by anticipating the results of long-latency instructions, including critical Loads. On the other hand, hiding instructions ’ long latencies in a pipelined superscalar processor represents an important challenge itself. We developed a superscalar architecture that selectively anticipates the values produced by high-latency instructions. In this work we are focusing on Multiply