Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration

Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the performance benefits of reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework achieves this by: (1) providing a means for choosing suitable custom instruction selection heuristics, (2) leveraging FPGA-aware merging of custom instructions to maximize the reconfigurable logic block utilization in each configuration, and (3) incorporating a hierarchical loop partitioning strategy to reduce runtime reconfiguration overhead. We show that the performance gain can be improved by employing suitable custom instruction selection heuristics that, in turn, depend on the reconfigurable resource constraints and the merging factor (extent to which the selected custom instructions can be merged). The hierarchical loop partitioning strategy leads to an average performance gain of over 31% and 46% for full and partial runtime reconfiguration, respectively. Performance gain can be further increased to over 52% and 70% for full and partial runtime reconfiguration, respectively, by exploiting FPGA-aware merging of custom instructions.</jats:p

Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration

Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the advantages of runtime reconfiguration on reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework incorporates a hierarchical loop partitioning strategy that leverages FPGA-aware merging of custom instructions to: 1) maximize the reconfigurable logic block utilization in each configuration, and 2) reduce the runtime reconfiguration overhead. Experimental results show that the proposed strategy leads to over 39% average reduction in runtime reconfiguration overhead for partial runtime reconfiguration. In addition, the proposed strategy leads to an average performance gain of over 32% and 34% for full and partial runtime reconfiguration respectively