11,333 research outputs found
Spectrum Sharing in mmWave Cellular Networks via Cell Association, Coordination, and Beamforming
This paper investigates the extent to which spectrum sharing in mmWave
networks with multiple cellular operators is a viable alternative to
traditional dedicated spectrum allocation. Specifically, we develop a general
mathematical framework by which to characterize the performance gain that can
be obtained when spectrum sharing is used, as a function of the underlying
beamforming, operator coordination, bandwidth, and infrastructure sharing
scenarios. The framework is based on joint beamforming and cell association
optimization, with the objective of maximizing the long-term throughput of the
users. Our asymptotic and non-asymptotic performance analyses reveal five key
points: (1) spectrum sharing with light on-demand intra- and inter-operator
coordination is feasible, especially at higher mmWave frequencies (for example,
73 GHz), (2) directional communications at the user equipment substantially
alleviate the potential disadvantages of spectrum sharing (such as higher
multiuser interference), (3) large numbers of antenna elements can reduce the
need for coordination and simplify the implementation of spectrum sharing, (4)
while inter-operator coordination can be neglected in the large-antenna regime,
intra-operator coordination can still bring gains by balancing the network
load, and (5) critical control signals among base stations, operators, and user
equipment should be protected from the adverse effects of spectrum sharing, for
example by means of exclusive resource allocation. The results of this paper,
and their extensions obtained by relaxing some ideal assumptions, can provide
important insights for future standardization and spectrum policy.Comment: 15 pages. To appear in IEEE JSAC Special Issue on Spectrum Sharing
and Aggregation for Future Wireless Network
Fundamental Limits in MIMO Broadcast Channels
This paper studies the fundamental limits of MIMO broadcast channels from a high level, determining the sum-rate capacity of the system as a function of system paramaters, such as the number of transmit antennas, the number of users, the number of receive antennas, and the total transmit power. The crucial role of channel state information at the transmitter is emphasized, as well as the emergence of opportunistic transmission schemes. The effects of channel estimation errors, training, and spatial correlation are studied, as well as issues related to fairness, delay and differentiated rate scheduling
Neural Collective Entity Linking
Entity Linking aims to link entity mentions in texts to knowledge bases, and
neural models have achieved recent success in this task. However, most existing
methods rely on local contexts to resolve entities independently, which may
usually fail due to the data sparsity of local information. To address this
issue, we propose a novel neural model for collective entity linking, named as
NCEL. NCEL applies Graph Convolutional Network to integrate both local
contextual features and global coherence information for entity linking. To
improve the computation efficiency, we approximately perform graph convolution
on a subgraph of adjacent entity mentions instead of those in the entire text.
We further introduce an attention scheme to improve the robustness of NCEL to
data noise and train the model on Wikipedia hyperlinks to avoid overfitting and
domain bias. In experiments, we evaluate NCEL on five publicly available
datasets to verify the linking performance as well as generalization ability.
We also conduct an extensive analysis of time complexity, the impact of key
modules, and qualitative results, which demonstrate the effectiveness and
efficiency of our proposed method.Comment: 12 pages, 3 figures, COLING201
Boosting Multi-Core Reachability Performance with Shared Hash Tables
This paper focuses on data structures for multi-core reachability, which is a
key component in model checking algorithms and other verification methods. A
cornerstone of an efficient solution is the storage of visited states. In
related work, static partitioning of the state space was combined with
thread-local storage and resulted in reasonable speedups, but left open whether
improvements are possible. In this paper, we present a scaling solution for
shared state storage which is based on a lockless hash table implementation.
The solution is specifically designed for the cache architecture of modern
CPUs. Because model checking algorithms impose loose requirements on the hash
table operations, their design can be streamlined substantially compared to
related work on lockless hash tables. Still, an implementation of the hash
table presented here has dozens of sensitive performance parameters (bucket
size, cache line size, data layout, probing sequence, etc.). We analyzed their
impact and compared the resulting speedups with related tools. Our
implementation outperforms two state-of-the-art multi-core model checkers (SPIN
and DiVinE) by a substantial margin, while placing fewer constraints on the
load balancing and search algorithms.Comment: preliminary repor
Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency
Persistent memory provides high-performance data persistence at main memory.
Memory writes need to be performed in strict order to satisfy storage
consistency requirements and enable correct recovery from system crashes.
Unfortunately, adhering to such a strict order significantly degrades system
performance and persistent memory endurance. This paper introduces a new
mechanism, Loose-Ordering Consistency (LOC), that satisfies the ordering
requirements at significantly lower performance and endurance loss. LOC
consists of two key techniques. First, Eager Commit eliminates the need to
perform a persistent commit record write within a transaction. We do so by
ensuring that we can determine the status of all committed transactions during
recovery by storing necessary metadata information statically with blocks of
data written to memory. Second, Speculative Persistence relaxes the write
ordering between transactions by allowing writes to be speculatively written to
persistent memory. A speculative write is made visible to software only after
its associated transaction commits. To enable this, our mechanism supports the
tracking of committed transaction ID and multi-versioning in the CPU cache. Our
evaluations show that LOC reduces the average performance overhead of memory
persistence from 66.9% to 34.9% and the memory write traffic overhead from
17.1% to 3.4% on a variety of workloads.Comment: This paper has been accepted by IEEE Transactions on Parallel and
Distributed System
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