4 research outputs found
Deploying Hard Real-Time Control Software on Chip-Multiprocessors
AbstractβDeploying real-time control systems software on multiprocessors requires distributing tasks on multiple processing nodes and coordinating their executions using a protocol. One such protocol is the discrete-event (DE) model of computation. In this paper, we investigate distributed discrete-event (DE) with null-message protocol (NMP) on a multicore system for real-time control software. We illustrate analytically and experimentally that even with the null-message deadlock avoidance scheme in the protocol, the system can deadlock due to inter-core message dependencies. We identify two central reasons for such deadlocks: 1) the lack of an upper-bound on packet transmission rates and processing capability, and 2) an unknown upper-bound on the communication network delay. To address these, we propose using architectural features such as timing control and real-time network-on-chips to prevent such message-dependent deadlocks. We employ these architectural techniques in conjunction with a distributed DE strategy called PTIDES for an illustrative car wash station example and later follow it with a more realistic tunnelling ball device application
Efficient State Retention for Transiently-powered Embedded Sensing
We present state retention techniques to support embedded sensing applications on 32-bit microcontrollers whose energy provisioning is assisted through ambient harvesting or wireless energy transfer. As energy availability is likely erratic in these settings, applications may be unpredictably interrupted. To behave dependably, applications should resume from where they left as soon as energy is newly available. We investigate the fundamental building block necessary to this end, and conceive three mechanisms to checkpoint and restore a device's state on stable storage quickly and in an energy-efficient manner. The problem is unique in many regards; for example, because of the distinctive performance vs. energy trade-offs of modern 32-bit microcontrollers and the peculiar characteristics of current flash chips. Our results, obtained from real experiments using two different platforms, crucially indicate that there is no ``one-size-fits-all'' solution. The performance depends on factors such as the amount of data to handle, how in memory the data is laid out, as well as an application's read/write patterns
MARTE/pCCSL: Modeling and Refining Stochastic Behaviors of CPSs with Probabilistic Logical Clocks
Best Paper AwardInternational audienceCyber-Physical Systems (CPSs) are networks of heterogeneous embedded systems immersed within a physical environment. Several ad-hoc frameworks and mathematical models have been studied to deal with challenging issues raised by CPSs. In this paper, we explore a more standard-based approach that relies on SysML/MARTE to capture different aspects of CPSs, including structure, behaviors, clock constraints, and non-functional properties. The novelty of our work lies in the use of logical clocks and MARTE/CCSL to drive and coordinate different models. Meanwhile, to capture stochastic behaviors of CPSs, we propose an extension of CCSL, called pCCSL, where logical clocks are adorned with stochastic properties. Possible variants are explored using Statistical Model Checking (SMC) via a transformation from the MARTE/pCCSL models into Stochastic Hybrid Automata. The whole process is illustrated through a case study of energy-aware building, in which the system is modeled by SysML/MARTE/pCCSL and different variants are explored through SMC to help expose the best alternative solutions
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볡μ λͺ¨λ λ©ν°λ―Έλμ΄ ν°λ―Έλ μμ λ₯Ό ν΅ν κΈ°μ΄μ μΈ μ€νλ€μ ν΅ν΄, μ μνλ λ°©λ²λ‘ μ νλΉμ±μ 보μΈλ€.As the number of processors in a chip increases, and more functions are integrated, the system status will change dynamically due to various factors such as the workload variation, QoS requirement, and unexpected component failure. On the other hand, computation-complexity of user applications is also steadily increasingvideo and graphics applications are two major driving forces in smart mobile devices, which define the main application domain of interest in this dissertation. So, a systematic design methodology is highly required to implement such complex systems which contain dynamically changed behavior as well as computation-intensive workload that can be parallelized.
A model-based approach is one of representative approaches for parallel embedded software development. Especially, HOPES framework is proposed which is a design environment for parallel embedded software supporting the overall design steps: system specification, performance estimation, design space exploration, and automatic code generation. Distinguished from other design environments, it introduces a novel concept of programming platform, called CIC (Common Intermediate Code) that can be understood as a generic execution model of heterogeneous multiprocessor architecture. The CIC task model is based on a process network model, but it can be refined to the SDF (Synchronous Data Flow) model, since it has a very desirable features for static analyzability as well as parallel processing. However, the SDF model has a typical weakness of expression capability, especially for the system-level specification and dynamically changed behavior of an application.
To overcome this weakness, in this dissertation, we propose an extended CIC task model based on dataflow and FSM models to specify the dynamic behavior of the system distinguishing inter- and intra-application dynamism. At the top-level, each application is specified by a dataflow task and the dynamic behavior is modeled as a control task that supervises the execution of applications. Inside a dataflow task, it specifies the dynamic behavior using a similar way as FSM-based SADFan SDF task may have multiple behaviors and a tabular specification of an FSM, called MTM (Mode Transition Machine), describes the mode transition rules for the SDF graph. We call it to MTM-SDF model which is classified as multi-mode dataflow models in the dissertation. It assumes that an application has a finite number of behaviors (or modes) and each behavior (mode) is represented by an SDF graph. It enables us to perform compile-time scheduling of each graph to maximize the throughput varying the number of allocated processors, and store the scheduling information.
Also, a multiprocessor scheduling technique is proposed for a multi-mode dataflow graph. While there exist several scheduling techniques for multi-mode dataflow models, no one allows task migration between modes. By observing that the resource requirement can be additionally reduced if task migration is allowed, we propose a multiprocessor scheduling technique of a multi-mode dataflow graph considering task migration between modes. Based on a genetic algorithm, the proposed technique schedules all SDF graphs in all modes simultaneously to minimize the resource requirement. To satisfy the throughput constraint, the proposed technique calculates the actual throughput requirement of each mode and the output buffer size for tolerating throughput jitter.
For the specified task graph and scheduling results, the CIC translator generates parallelized code for the target architecture. Therefore the CIC translator is extended to support extended features of the CIC task model. In application-level, it is extended to support multiprocessor code generation for an MTM-SDF graph considering the given static scheduling results. Also, multiprocessor code generation of four different scheduling policies are supported for an MTM-SDF graph: fully-static, self-timed, static-assignment, and fully-dynamic. In system-level, the CIC translator is extended to support code generation for implementation of system request APIs and data structures for the static scheduling results and configurable task parameters.
Through preliminary experiments with a multi-mode multimedia terminal example, the viability of the proposed methodology is verified.Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Contribution 7
1.3 Dissertation organization 9
Chapter 2 Background 10
2.1 Related work 10
2.1.1 Compiler-based approach 10
2.1.2 Language-based approach 11
2.1.3 Model-based approach 15
2.2 HOPES framework 19
2.3 Common Intermediate Code (CIC) Model 21
Chapter 3 Dynamic Behavior Specification 26
3.1 Problem definition 26
3.1.1 System-level dynamic behavior 26
3.1.2 Application-level dynamic behavior 27
3.2 Related work 28
3.3 Motivational example 31
3.4 Control task specification for system-level dynamism 33
3.4.1 Internal specification 33
3.4.2 Action scripts 38
3.5 MTM-SDF specification for application-level dynamism 44
3.5.1 MTM specification 44
3.5.2 Task graph specification 45
3.5.3 Execution semantic of an MTM-SDF graph 46
Chapter 4 Multiprocessor Scheduling of an Multi-mode Dataflow Graph 50
4.1 Related work 51
4.2 Motivational example 56
4.2.1 Throughput requirement calculation considering mode transition delay 56
4.2.2 Task migration between mode transition 58
4.3 Problem definition 61
4.4 Throughput requirement analysis 65
4.4.1 Mode transition delay 66
4.4.2 Arrival curves of the output buffer 70
4.4.3 Buffer size determination 71
4.4.4 Throughput requirement analysis 73
4.5 Proposed MMDF scheduling framework 75
4.5.1 Optimization problem 75
4.5.2 GA configuration 76
4.5.3 Fitness function 78
4.5.4 Local optimization technique 79
4.6 Experimental results 81
4.6.1 MMDF scheduling technique 83
4.6.2 Scalability of the Proposed Framework 88
Chapter 5 Multiprocessor Code Generation for the Extended CIC Model 89
5.1 CIC translator 89
5.2 Code generation for application-level dynamism 91
5.2.1 Function call-style code generation (fully-static, self-timed) 94
5.2.2 Thread-style code generation (static-assignment, fully-dynamic) 98
5.3 Code generation for system-level dynamism 101
5.4 Experimental results 105
Chapter 6 Conclusion and Future Work 107
Bibliography 109
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