A software test program generator for verifying system-on-chips

© 2005 IEEE.Design verification is crucial for successful systems-on-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a technique to test the SoC at the system level using software application based programs. Our software application level verification methodology (SALVEM) employs test programs composed of dynamic sequences of software code segments. The SALVEM system implements a test generator to create these software test programs automatically. Experiments were conducted applying SALVEM tests to the Altera Nios SoC. A feedback verification flow is also feasible in our SALVEM system. SALVEM test runs are analyzed to direct the test generator toward important SoC scenarios.Cheng, A.; Cheng-Chew Lim; Parashkevov, A

Evolutionary Test Program Induction for Microprocessor Design Verification

Design verification is a crucial step in the design of any electronic device. Particularly when microproces-sor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a test pro-gram for maximizing a given verification metric. The methodology is based on an evolutionary paradigm and exploits a syntactical description of microprocessor assembly language and an RT-level functional model. Experimental results show the effectiveness of the ap-proach. 1