2 research outputs found
Equalization-Based Digital Background Calibration Technique for Pipelined ADCs
In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC
Bi-Linear Homogeneity Enforced Calibration for Pipelined ADCs
Pipelined analog-to-digital converters (ADCs) are key enablers in many
state-of-the-art signal processing systems with high sampling rates. In
addition to high sampling rates, such systems often demand a high linearity. To
meet these challenging linearity requirements, ADC calibration techniques were
heavily investigated throughout the past decades. One limitation in ADC
calibration is the need for a precisely known test signal. In our previous
work, we proposed the homogeneity enforced calibration (HEC) approach, which
circumvents this need by consecutively feeding a test signal and a scaled
version of it into the ADC. The calibration itself is performed using only the
corresponding output samples, such that the test signal can remain unknown. On
the downside, the HEC approach requires the option to accurately scale the test
signal, impeding an on-chip implementation. In this work, we provide a thorough
analysis of the HEC approach, including the effects of an inaccurately scaled
test signal. Furthermore, the bi-linear homogeneity enforced calibration
(BL-HEC) approach is introduced and suggested to account for an inaccurate
scaling and, therefore, to facilitate an on-chip implementation. In addition, a
comprehensive stability and convergence analysis of the BL-HEC approach is
carried out. Finally, we verify our concept with simulations.Comment: 12 pages, 5 figure