ENHANCING TESTABILITY IN ARCHITECTURAL DESIGN FOR THE NEW GENERATION OF CORE-BASED EMBEDDED SYSTEMS

This paper proposes testability enhancements in architectural design for embedded cores-based system-on-a-chip (SoC). There exist methods to ensure correct SoC functionality in both hardware and software, but one of the most reliable ways to realize this is through the use of design for testability approaches. Specifically, applications of built-in self-test (BIST) methodology for testing embedded cores are considered in the paper, with specific implementations being targeted towards ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. I